Versal ACAP Clocking Resources Architecture Manual (AM003)

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1.4 English

The BUFGCE_1 primitive is a clock buffer with one clock input, one clock output, and a clock enable line. This primitive is based on BUFGCTRL with some pins connected to logic High or Low. The following figure illustrates the relationship of BUFGCE_1 and BUFGCTRL. The LOC constraint is available for manually placing the BUFGCE_1 location. See the Vivado Design Suite User Guide: Using Constraints (UG903) for more information.

Figure 1. BUFGCE_1 using BUFGCTRL
Important: The select signal must meet the setup time requirement because the clock enable line uses the CE pin of the BUFGCTRL. Violating this setup time can result in a glitch.

The following figure illustrates the timing diagram for BUFGCE_1.

Figure 2. BUFGCE_1 Timing Diagram