Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
Release Date
1.4 English

BUFGCE_DIV is a clock buffer with one clock input (I), one clock output (O), one clear input (CLR), and a clock enable (CE) input. BUFGCE_DIV can directly drive the routing and distribution resources and is a clock buffer with a single gated input and a reset. Its O output is 0 when CLR is High (active). When CE is High, the I input is transferred to the O output. CE is synchronous to the clock for glitch-free operation. CLR is an asynchronous reset assertion and synchronous reset deassertion to this buffer. BUFGCE_DIV can also divide the input clock by 1 to 8.

When CLR (reset) is deasserted, the output clock transitions from Low to High on the first edge after the CLR is deasserted, regardless of the divide value. Therefore, BUFGCE_DIV output clocks are always aligned, regardless of the divide value. The output clock then toggles at the divided frequency. When CLR is asserted, the clock stops toggling after some clock-to-out time. For an odd divide, the duty cycle is not 50% because the clock is High one cycle less than it is Low. For example, for a divide value of 7, the clock is High for 3 cycles and Low for 4 cycles.

When CE is deasserted, the output stops at its current state, High or Low. When CE is reasserted, the internal counter restarts from where it stopped. For example, if the divide value is 8 and CE is deasserted two input clock cycles after the last output High transition, the output stays High. Then when CE is reasserted, the output transitions Low after two input clock cycles. If the reset input is used, upon assertion the output transitions Low immediately if the current output is High, otherwise it stays Low.

Because reset is synchronously deasserted, when reset is deasserted in the previous example, the output transitions High at the next input clock edge and transitions Low four input clock cycles later.

The following table shows the BUFGCE_DIV pins.

Table 1. BUFGCE_DIV Pins
Pin Name Type Invertible Description
I Input FALSE Clock input
CLR Input TRUE Reset
CE Input TRUE Clock enable
O Output FALSE Clock output

The following table shows the BUFGCE_DIV attributes.

Table 2. BUFGCE_DIV Attributes
Attribute Name Values Default Type Description
BUFGCE_DIVIDE 1, 2, 3, 4, 5, 6, 7, 8 1 Integer Defines whether the output clock is a divided version of the input clock.
CE_TYPE SYNC,HARDSYNC SYNC STRING Sets the clock enable behavior where SYNC allows for a glitch-less transition. The SYNC setting times the CE pin in the Vivado tools. HARDSYNC turns ON an internal 3-stage synchronizer for maximum performance. However, that results in a latency of either three or four clock cycles.
HARDSYNC_CLR FALSE, TRUE FALSE STRING Asynchronous clear port to control CLR_B signal on BUFDIV_LEAF
STARTUP_SYNC FALSE, TRUE FALSE STRING Defines whether logic to CE input is staged
Note: For additional tool related attributes used by Vivado Design Suite during the opt_design stage, refer to the Versal Architecture AI Core Series Libraries Guide (UG1353).

The following figure shows the BUFGCE_DIV timing diagram.

Figure 1. BUFGCE_DIV Timing Diagram