BUFGCTRL

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
AM003
Release Date
2022-05-24
Revision
1.4 English

The BUFGCTRL primitive shown in the following figure can switch between two asynchronous clocks. All other global clock buffer primitives are derived from certain configurations of BUFGCTRL. BUFGCTRL has four select lines, S0, S1, CE0, and CE1. It also has two additional control lines, IGNORE0 and IGNORE1. These six control lines are used to control the inputs I0 and I1.

Figure 1. BUFGCTRL Primitive

BUFGCTRL is designed to switch between two clock inputs without the possibility of a glitch. When the presently selected clock transitions from High to Low after S0 and S1 change, the output is kept Low until the other (to-be-selected) clock transitions from High to Low. Then the new clock starts driving the output. The default configuration for BUFGCTRL is falling-edge sensitive and held at Low prior to the input switching. BUFGCTRL can also be rising-edge sensitive and held at High prior to the input switching by using the INIT_OUT attribute.

In some applications, the conditions previously described are not desirable. Asserting the IGNORE pins bypasses the BUFGCTRL from detecting the conditions for switching between two clock inputs. In other words, asserting IGNORE causes the MUX to switch the inputs at the instant the select pin changes. IGNORE0 causes the output to switch away from the I0 input immediately when the select pin changes, while IGNORE1 causes the output to switch away from the I1 input immediately when the select pin changes.

Selection of an input clock requires a “select” pair (S0 and CE0, or S1 and CE1) to be asserted High. If either S or clock enable (CE) is not asserted High, the desired input is not selected. In normal operation, both S and CE pairs (all four select lines) are not expected to be asserted High simultaneously. Typically, only one pin of a “select” pair is used as a select line, while the other pin is tied High. The truth table is shown in the following table.

Table 1. Truth Table for BUFGCTRL Clocking Resources
CE0 S0 CE1 S1 O
1 1 0 X I0
1 1 X 0 I0
0 X 1 1 I1
X 0 1 1 I1
1 1 1 1 Old Input 1
  1. Old input refers to the valid input clock before this state is achieved.
  2. For all other states, the output becomes the value of INIT_OUT and does not toggle.

Although both S and CE are used to select a desired output, only S is suggested for glitch-free switching. This is because when using CE to switch clocks, the change in clock selection can be faster than when using S. A violation in the setup/hold time of the CE pins causes a glitch at the clock output. On the other hand, using the S pins allows the user to switch between the two clock inputs without regard to setup/hold times. As a result, using S to switch clocks does not result in a glitch. See BUFGMUX_CTRL.

The following timing diagram illustrates various clock switching conditions using the BUFGCTRL primitives. Exact timing numbers are best found using the speed specification.

Figure 2. BUFGCTRL Timing Diagram
  • Before time event 1, output O uses input I0.
  • At time TBCCCK_CE, before the rising edge at time event 1, both CE0 and S0 are deasserted Low. At about the same time, both CE1 and S1 are asserted High.
  • At time TBCCKO_O, after time event 3, output O uses input I1. This occurs after a High-to-Low transition of I0 (event 2) followed by a High-to-Low transition of I1.
  • At time event 4, IGNORE1 is asserted.
  • At time event 5, CE0 and S0 are asserted High while CE1 and S1 are deasserted Low. At TBCCKO_O, after time event 6, output O has switched from I1 to I0 without requiring a High-to-Low transition of I1.

Other capabilities of the BUFGCTRL primitive are:

  • Pre-selection of the I0 and I1 inputs are made after configuration but before device operation.
  • The initial output after configuration can be selected as either High or Low.
  • Clock selection using CE0 and CE1 only (S0 and S1 tied High) can change the clock selection without waiting for a High-to-Low transition on the previously selected clock.

The following table summarizes the attributes for the BUFGCTRL primitive.

Table 2. BUFGCTRL Attributes
Attribute Name Description Possible Values
INIT_OUT Initializes the BUFGCTRL output to the specified value after configuration. Sets the positive or negative edge behavior. Sets the output level when changing clock selection. 0 (default), 1
PRESELECT_I0 If TRUE, BUFGCTRL output uses the I0 input after configuration. 1 FALSE (default), TRUE
PRESELECT_I1 If TRUE, BUFGCTRL output uses the I1 input after configuration. 1 FALSE (default), TRUE
  1. Both PRESELECT attributes cannot be TRUE at the same time.