Clock Buffers

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
AM003
Release Date
2022-05-24
Revision
1.4 English

Global clocks are a dedicated network of interconnects specifically designed to reach all clock inputs to the various resources in a device. These networks are designed to have low skew and low duty cycle distortion, low power, and improved jitter tolerance. They are also designed to support very high-frequency signals.

Understanding the signal path for a global clock expands the understanding of the various global clocking resources. The global clocking resources and network consist of these paths and components:

  • Clock structure
  • Clock buffers
  • BUFGCTRL clock buffer primitives
  • Additional BUFGCTRL use models
  • BUFGCE and BUFGCE_DIV clock buffers
  • BUFG clock buffer
  • BUFG_GT clock buffer
  • BUFG_PS clock buffer
  • BUFG_FABRIC buffer (for routing high fanout non-clock nets, not a global clock resource)

All buffers are described later in this chapter.