Clock Buffers and Routing

Versal ACAP Clocking Resources Architecture Manual (AM003)

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1.4 English

Each XPIO I/O bank contains four global clock input pins (GCs) to bring user clocks onto the device clock management and routing resources. Every HDIO bank contains two GC pins. The global clock inputs bring user clocks onto:

  • XPLLs in the same bank (XPHY) and adjacent banks.
  • MMCM and DPLL next to the XPIO banks (XPHY).
  • Any of the 24 BUFGCEs, 8 BUFGCTRLs, and 4 BUFGCE_DIVs co-located with the MMCMs/DPLLs.
  • Two GC pins per HDIO bank can drive DPLLs and four clock buffers (only BUFGCE) next to them.

Each device has three general purpose global clock buffers: BUFGCTRL, BUFGCE, and BUFGCE_DIV. In addition, there is a local BUFDIV_LEAF clock buffer for driving leaf clocks from horizontal distribution to various blocks in the device. The BUFDIV_LEAF is a physical only buffer and cannot be instantiated by the user. BUFGCTRL has derivative software representations of types BUFGMUX, BUFGMUX1, BUFGMUX_CTRL, and BUFGCE_1. BUFGCE is for improved clock gating and has a software derivative BUFG (BUFGCE with clock enable tied High). The global clock buffers drive routing and distribution tracks into the device logic through the HCS rows. There are 12 routing and 24 distribution tracks in each HCS row. Bottom and top clocking rows have 24 routing and 24 distribution tracks. There is BUFG_PS that drives from PS through horizontal and vertical routing tracks and also BUFG_GT that generates divided clocks for GT clocking. The clock buffers:

  • Can be used as a clock enable circuit to enable or disable clocks either globally, locally, or within a CR for fine-grained power control
  • Can be used as a glitch-free multiplexer to:
    • Select between two clock sources
    • Switch away from a failed clock source
  • Are often driven by an MMCM/XPLL/DPLL to:
    • Eliminate the clock distribution delay
    • Adjust clock delay relative to another clock

See Versal Architecture Clocking Resources for further details on global clocks, I/O, and GT clocking. It also describes which clock routing resources to use for various applications.

In Versal ACAP, there is a new group of multi-clock buffers (MBUFG) that are similar to BUFGs but with multiple clock outputs. Refer to Multi-Clock Buffers.