Clock uncertainty or clock jitter, is highly dependent on the amount and spectrum of noise present on the power supply used for a clock distribution network. The power supply noise in Versal® ACAPs is dependent on the activity within the configurable logic. This makes it difficult to predict the jitter because each design has a unique amount of activity that produces a unique noise magnitude and spectrum.
One option to predict jitter is to assume the worst-case noise condition and apply that jitter to all designs. This approach is not recommended because it has the undesirable effect of applying the maximum penalty to all designs.
In Versal ACAPs, the global clock routing within the ACAP is powered by the RAM supply. The noise on the RAM supply is only dependent on the block RAM and UltraRAM (URAM) usage which helps bound the analysis.
This section describes what type of RAM activity creates noise on the power supply and methods that can be used to reduce this noise. It also covers how this jitter is modeled by the Vivado® Design Suite and defines some user inputs that can be used to reduce the clock uncertainty.