Clock Management MMCM, XPLL, and DPLL

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
AM003
Release Date
2022-05-24
Revision
1.4 English

Each device has MMCMs, DPLLs, and XPLLs near the PHY next to each of the I/O banks. An MMCM block consists of one MMCM and one DPLL. Other DPLLs reside next to HDIO and GT columns. The MMCM is the primary block for frequency synthesis for a wide range of frequencies, and serves as a jitter filter for either external or internal clocks, and deskews clocks among a wide range of other functions. Similar in basic functionalities and capabilities to the MMCMs and XPLLs, the DPLLs provide clock output to the general interconnect of the Xilinx® Versal adaptive compute acceleration platform (ACAPs). It can also be used for deskewing applications. The primary purpose of the XPLL is to provide clocking to the PHY I/Os, but it can also be used for clocking other resources in the device in a limited fashion. The device clock input connectivity allows multiple resources to provide the reference clock(s) to the MMCM and XPLL.

MMCMs, DPLLs, and XPLLs have infinite fine phase shift capability in either direction and can be used in dynamic phase shift mode. MMCM and DPLL have 26 resolution fractional feedback counters to generate output frequencies that are non-integer multiples of the reference clock frequency.

The LogiCORE™ IP clocking wizard is available to assist in using the MMCMs, DPLLs, and XPLLs to create clock networks in Xilinx Versal architecture designs. The GUI interface is used to collect clock network parameters. The clocking wizard chooses the appropriate clock resource and optimally configures the clock management resource and associated clock routing resources.

See Clock Management Functions for further details on the MMCM, XPLL, and DPLL block features and connectivity.

Clock Trees and Buffers

  • Vertical clocking spines are constructed as balanced binary trees. This operation equalizes delays to the horizontal spines for matching delays of the static clock networks.
  • Active clock deskews minimize jitter through a calibrated skew compensation to minimize local and global skews both within a die and between two SLRs. Refer to Clock Skew Minimization through Calibrated Mesh Network Deskew. This is achieved through an calibrated deskew mesh using phase detectors that modulate delays at clock region boundaries.
  • The leaf clocks no longer have EN pins but have added divide capability.
Figure 1. Locations of Clock Buffer Resources and Clock Management Functions