Versal architecture uses calibrated skew compensation system to minimize both local and global skew. This is effectively a global clock calibration executed while the part is powered up. A Versal ACAP then automatically adjusts the insertion delay of clocks of each CR to minimize effects of process variations across the die. It samples phase information at all active CR boundaries, and modulates delay lines consisting of coarse and fine delays to each CR to match with all of its neighbors. Delay lines are initialized at configuration time. Prior to the startup of the device, PDs at the CR boundaries measure phase-offset from their neighbors. This information is relayed back to the state machines controlling the delay lines for the two clocks. A simple up/down indication is sent to the surrounding CR’s PDs. If information from all PDs agree which way to move (increment/decrement delay), the delay line controller updates the fine delays. This adaptive deskew mesh network then converges on an optimal solution. The adaptive deskew system is bypass-able in the event that it is preferred to route a clock signal with minimal delay insertion (I/O interfaces or parallel BUFG when implementing synchronous clock domain crossings).
Note: In Vivado® tools 2021.2.x, calibrated deskew is disabled by default because timing can have incorrect skew results. If you are using Vivado tools 2021.1 and 2021.1.1, you will have to apply a patch and re-implement the design. Check with field support for additional details. Refer to Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387) for details on how to use the GCLK_DESKEW property to enable/disable calibrated deskew.