The following table lists the attributes for the DPLL primitive.
|CLKOUT[0:3]_DIVIDE||Decimal||2 to 511||2||Specifies the amount to divide the associated CLKOUT clock output if a different frequency is desired. This number, in combination with the CLKFBOUT_MULT_F and DIVCLK_DIVIDE values, determines the output frequency.|
|CLKOUT[0:3]_PHASE||Real||–360.000 to 360.000||0.000||Specifies the output phase relationship of the associated CLKOUT clock output in number of degrees offset (that is, 90 indicates a 90° or ¼ cycle offset phase offset while 180 indicates a 180° offset or ½ cycle phase offset). In static phase shift mode, the minimum phase step resolution (degrees) = (360/CLKOUT[0:3]_DIVIDE)/8|
|CLKFBOUT_MULT||Decimal||10 to 400||42||Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, determines the output frequency.|
|CLKFBOUT_FRACT||Decimal||0 to 63||0||6-bit fractional M feedback divider in increments of 1/63. Generates a fraction of the CLKFBOUT_MULT value and adds it to CLKFBOUT_MULT.|
|DIVCLK_DIVIDE||Decimal||1 to 123||1||Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD.|
|REF_JITTER||Real||0.000 to 0.200||0.010||Allows specification of the expected jitter on the reference clock to better optimize DPLL performance. If known, the value provided should be specified in terms of the unit interval (UI) (the maximum peak-to-peak value) of the expected jitter on the input clock.|
|CLKIN_PERIOD||Real||0.000 to 100.000||0.000||
Specifies the input period in ns to the DPLL CLKIN1 input.
Resolution is down to the ps. This information is mandatory and must be supplied.
|CLKOUTn_PHASE_CTRL[0:1]||Binary||00 to 11||00||
CLKOUT[0:3] counter variable fine phase shift or deskew select.
00: Interpolator is not controlled by either deskew or phase shift interface.
01: Interpolator is controlled by Deskew.
10: Interpolator is controlled by phase shift interface.
Other binary values are not valid.
|DESKEW_DELAY||Decimal||0 to 63||0||Value of the optional programmable delay in the deskew circuit.|
|DESKEW_DELAY_PATH||String||TRUE, FALSE||FALSE||Determines if the CLKIN_DESKEW path or the CLKFB_DESKEW path is selected for the optional programmable delay. TRUE = CLKFB_DESKEW, FALSE = CLKIN_DESKEW. If ZHOLD = TRUE, DESKEW_DELAY_PATH must be set to TRUE.|
|DESKEW_DELAY_EN||String||FALSE, TRUE||FALSE||Set to TRUE to enable the optional programmable delay in the deskew circuit. Must be set to TRUE if ZHOLD = TRUE.|
|ZHOLD||String||TRUE, FALSE||FALSE||Indicates the DPLL is configured to provide a negative hold time only at the HDIO registers.|
|LOCK_WAIT||String||FALSE, TRUE||FALSE||Wait during the configuration startup for the DPLL to lock.|
|PERF_MODE||STRING||LIMITED, FULL||LIMITED||Specifies DPLL performance mode. Must remain at the default setting (LIMITED) for non-deskew mode. The FULL mode is reserved for AMD IP use or clocking wizard implementation with digital deskew enabled for the Vivado 2022.1 tools. In the Vivado 2022.2 tools and after, it will be for with and without digital deskew.|