DPLL Ports

Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)

Document ID

AM003

Release Date

2023-05-16

Revision

1.5 English

The following table summarizes the DPLL ports.

Table 1. DPLL Ports
Port Name	I/O	Description
CLKIN1	Input	General clock input.
RST	Input	Asynchronous reset signal. The RST signal is an asynchronous reset for the DPLL. The DPLL synchronously re-enables itself when this signal is released (that is, DPLL re-enabled). A reset is required when the input clock conditions change (for example, frequency).
PWRDWN	Input	Powers down instantiated but unused DPLLs.
CLKOUT[0:3]	Output	User configurable clock outputs (0 through 3) that can be divided versions of the VCO phase outputs (user controllable) from 2 to 512. The output clocks are phase aligned to each other (unless phase shifted) and aligned to the input clock with a proper feedback configuration.
CLKIN_DESKEW	Input	Primary clock input to the phase detector1 block for deskewing clock network delays between two different CLKOUT networks.
CLKFB_DESKEW	Input	Secondary (feedback) clock input to the phase detector1 block for deskewing clock network delays
LOCKED_FB	Output	An output from the DPLL that indicates when the DPLL has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The DPLL automatically locks after power on. No extra reset is required. LOCKED is deasserted if the input clock stops or the phase alignment is violated (for example, input clock phase shift). The DPLL must be reset after LOCKED is deasserted.
LOCKED1/2_DESKEW	Output	Indicates if the deskew circuit is locked. Applies only to the deskew circuits used in the design. Ignore these outputs for unused deskew circuits.
LOCKED	Output	The LOCKED signal indicates that all functions requiring a LOCKED signal for the DPLL to operate properly have LOCKED. This LOCKED signal is therefore an AND function of LOCKED_FB and both LOCKED1/2_DESKEWs if used.
DO[15:0]	Output	The dynamic reconfiguration output bus provides DPLL data output when using dynamic reconfiguration.
DI[15:0]	Input	The dynamic reconfiguration data input (DI) bus provides reconfiguration data. When not used, all bits must be set to zero.
DADDR[6:0]	Input	The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros.
DRDY	Output	The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the DPLL’s dynamic reconfiguration feature.
DWE	Input	The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it must be tied Low.
DEN	Input	The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low.
DCLK	Input	The DCLK signal is the reference clock for the dynamic reconfiguration port.
PSCLK	Input	Phase shift clock.
PSEN	Input	Phase shift enable.
PSINCDEC	Input	Phase shift increment/decrement control.
PSDONE	Output	Phase shift done.
All control and status signals except PSINCDEC are active-High.

Tip: The port names generated by the clocking wizard can differ from the port names used on the primitive.

For dynamic reconfiguration port description, see Dynamic Reconfiguration Port (DRP). For all other port descriptions, refer to the MMCM Port Descriptions.