Versal ACAP is equipped with functionality to allow the deskewing of the MMCM, DPLL, and/or XPLL output clocks.
- These deskew options do not
replace the classic feedback of MMCM, DPLL, and/or XPLL.
Normal MMCM and PLL feedback uses an M counter with clock feedback output (CLKFBOUT) that needs to be routed/connected to the clock feedback input (CLKFBIN). This feedback route can be direct, pass through a clock buffer, or is internal or external.
- The deskew inputs and logic (Phase Detector (PD) and Phase Interpolator (PI)) help align and deskew an output clock network ( CLKOUT*), and to provide an input clock other than the regular input clock (CLKIN). The deskew functionality is aimed at eliminating the skew between two clock networks of the same frequency. See Functioning of Deskew for additional details.
- The deskew function operates by using a PD on two clocks inputs and a set of PIs. There is one PI for each output counter and therefore a clock output as in the figure below. Each PI can be controlled by a PD.
- The PD looks to align the rising edge of the both input clocks (CLKIN_DESKEW and CLKFB_DESKEW). The output of the PD controls the selected PIs to output one of 32 VCO clock phases to the required output counter. A configurable delay line with selectable input (CLKIN_DESKEW or CLKFB_DESKEW) can be inserted in one of the two inputs of the PD. The delay line has a fixed input delay and consists of 64 taps of 40 ps (PVT variable) each.
- The PI converts the eight clock phases coming from the VCO to 32
phases feeding the output counters O and M under control of a PD.
- The PI in front of an output counter selects one of 32 phases as the clock for the output.
- Eight VCO phase equals to 45° for each phase, 32 phases equals to 11.25° per phase. Therefore, it is absolutely necessary to have the VCO run as fast as possible to keep the phase jumps of 11.25° as small as possible for lower speed output clocks.
- The fine phase shift option of an MMCM also uses the PI to do its job.