The concept of a heterogeneous clock management tile (CMT) no longer exists and its functions are separated in to the XPLL, MMCM/DPLL, and GCLK blocks. The XPLL and MMCM have been separated and are located in the optimal position for the Versal architecture. The main function of the XPLL is to clock the XPHY that are embedded within the XPIO banks. The MMCM is still co-located with the clock buffers.
- Includes two deskew subsystems each containing a deskew phase detector (PD). The deskew PD can adjust the phase of the output counters through the phase interpolators (PIs) to deskew the delay between two clock inputs connected to CLKIN/CLKFB, connected to the inputs of the same deskew PD. When used to deskew, the PIs cannot be used in the fine phase-shift mode.
- Each output counter of the MMCM has a PI associated with it. The PI is placed between the VCO and the counter and can provide static or dynamic fine phase shifting of the counter inputs. The resolution of phase shift is now 1/32 of the VCO clock.
- The UltraScale device method of fractional divide has been replaced with a sigma-delta module (SDM) based fractional mode. The MMCM now supports fractional divide ratios with a 6-bit resolution which is much finer than the 0.125 resolution that was supported in the UltraScale device. This fractional divide is supported using CLKFBOUT. CLKOUT0 no longer has support for fractional divide.
- The ZHOLD compensation mode has been removed from MMCM because XPIO no longer supports the legacy memory interface mode. ZHOLD is supported by the DPLL for the HDIO columns.
- The complementary (inverted) outputs have been removed from the counters.
- The clock divide dynamic change (CDDC) feature whereby you can change the output counter divide ratio using Dynamic Reconfiguration Port (DRP) has been removed.
- The Startup Wait option during configuration has been eliminated.
- Dynamic configuration in MMCM and/or PLL is performed through the Dynamic Reconfiguration Port. Unlike UltraScale devices, an APB3-compatible interface is the only option used as the protocol on DRP signals. Refer to Dynamic Reconfiguration Port (DRP) for more details.
- Wider multiply and divide ranges and other data sheet specification improvements.
- The user must re-implement the MMCM and PLL designs from a prior family in the Versal device. The Vivado tools migrate, for example, the MMCME4_ADV and PLLE4_ADV primitives from prior families to the MMCME5 and XPLL primitives, respectively, but the results must be reviewed. Some prior family primitives are not supported in Versal primitives, and the migrated settings are likely to be sub-optimal for the Versal primitives. See the Clocking Wizard for Versal Adaptive SoC LogiCORE IP Product Guide (PG321) for additional information.
- The name of the PLL has changed to XPLL. XPLL is used for every DDR interface along with XPHY.
- Specification improvements as detailed in the Versal adaptive SoC data sheets listed in References.
- There are four output counters (dividers) instead of two that support programmable logic clocking. The complementary (inverted) outputs have been removed.
- The XPLL functionality is extended by a user-controllable deskew subsystem. This system allows that an output clock can be dynamically deskewed or phase shifted to an input clock other than the required XPLL input clock.
- The XPLL can be set up to deskew the delay between the two clock inputs connected to CLKIN_DESKEW/CLKFB similar to MMCM.
- The XPLL now has a dynamic phase shift capability and dynamic phase shift interface for each output and feedback counter. Resolution of this phase shift is 1/32 of the VCO clock.
An MMCM Lite version of the PLL (DPLL) block has been added.
- The DPLL is located next to the HDIO banks and GT banks.
- The functionality and capabilities of the DPLL are similar to that of the MMCM. The DPLL is also located next to every MMCM to provide an increased number of clocking managers.
- The primary function is for frequency synthesis. Duty cycle is not programmable.
- All operations are on a clock cycle basis.
Clock Jitter due to Memory Resource Activity
In previous generations, the global clock (GCLK) network operates on VCCINT power domain. However, with Versal devices, the GCLK network and RAM primitives share a power supply (VCC_RAM). The noise on the RAM supply (BRAM and UltraRAMs), caused by the RAMs turning ON and OFF, can increase the clock jitter. This additional jitter is modeled and reported by Vivado tools. Users can apply a script-generated parameter to override the default value and reduce the impact of clock jitter due to GCLK activity. For a detailed explanation of the GCLK jitter introduced and the methodology to reduce the impact, see Clock Jitter Due to Memory Resource Activity and the associated script.