Dynamic Reconfiguration Port (DRP)

Versal ACAP Clocking Resources Architecture Manual (AM003)

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In most circumstances, MMCM and/or PLL used in a design are configured using static-calculated values to set up the used outputs. A wizard can be used to calculate all values and generate a instantiable wrapper containing a configured MMCM or PLL or one can instantiate the MMCM and/or PLL primitive and calculate the values separately to make the primitive function correctly using the formula given in this guide.

The DRP port provides the ability to use an MMCM and/or PLL as a dynamic element in a design. The DRP port setup is that of a common microcontroller peripheral and gives the user access to a set of registers in the MMCM or PLL. These registers allow the user to fully control the MMCM or PLL. Inputs pins and the values to define output clocks are turned into register bits making it possible to use the primitives as active elements in a design.

The DRP port connections and port descriptions are shown in the following figure and table.

Figure 1. DRP Port

Table 1. DRP Port Signals
Port Size I/O Description
DCLK 1 input The DCLK signal is the reference clock for the dynamic reconfiguration port. This clock is normally about 100 MHz to 200 MHz.
DEN 1 input The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low.
DWE 1 input The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the data on the DI port into the register selected by the DADDR address. When not used, DWE must be tied Low.
DADDR 7 input The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address to access a specific register in the primitive for dynamic reconfiguration. When not used, all bits must be assigned zeros.
DI 16 input The dynamic reconfiguration data input (DI) bus provides reconfiguration data that writes into a specified address (DADDR) of the register set. When not used, all bits must be set to zero.
DO 16 output The dynamic reconfiguration output bus provides data output of the register selected by the DADDR bus. This port can be used to read DRP register contents.
DRDY 1 output The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the PLL’s dynamic reconfiguration feature. This signal is pulsed High when a write or read operation is successful.

Unlike previous generations, the protocol on the DRP signals in Versal ACAPs has been changed to be an APB3-compatible interface. The table below shows the mapping between DRP and APB3 signals. Note that the APB3 PSEL signal is not supported, and thus, the MMCM or PLL DRP ports must be the only slave peripheral on an APB3 bus because the DRP interface is always selected and responds to all APB3 bus transactions.

Table 2. Mapping Between DRP and APB3 Signals
DRP signals APB3 signals I/O Size
DCLK PCLK input 1
DWE PWRITE input 1
DI PWDATA input 16
DOUT PRDATA output 16
DRDY PREADY output 1

It is strongly recommended to use clocking wizard to setup dynamic reconfiguration. When using the clocking wizard, the DRP port (running on the APB3 protocol) can be enabled via an AXI4-Lite controller. To see how the clocking wizard provides an AXI4-Lite interface for the dynamic reconfiguration of the clocking primitives MMCM/XPLL/DPLL, refer to the Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321).

The DRP port running on the APB3 protocol is intended to be used over standard AXI connections to simplify interface connections. Contact Xilinx support if the intended application cannot use the AXI protocol.

The APB3-compatible interface is based on the APB3 interface, which is described in the AMBA® APB Protocol Specification v2.0, together with read and write timing waveforms.