Frequency Synthesis without Deskew

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID: AM003
Release Date: 2022-05-24
Revision: 1.4 English

Overview
Introduction to Versal ACAP
Navigating Content by Design Process
Clocking Resources Features
Clock Buffers and Routing
Clock Management MMCM, XPLL, and DPLL
Differences from Previous Generations
Versal Architecture Clocking Resources
Global Clock Inputs
Clock Buffers
Clock Routing Structure and Resources
Clock Skew Minimization through Calibrated Mesh Network Deskew
Primitives
Clock Buffer Resources
BUFGCTRL Clock Buffer Primitives
BUFGCTRL
BUFGCE_1
BUFGMUX and BUFGMUX_1
BUFGMUX_CTRL
Additional BUFGCTRL Use Models
Asynchronous MUX Using BUFGCTRL
BUFGMUX_CTRL with a Clock Enable
BUFGCE Clock Buffers
BUFG Clock Buffer
BUFDIV_LEAF Clock Buffer
BUFGCE_DIV
BUFG_GT and BUFG_GT_SYNC
Multi-Clock Buffers
BUFG_PS
BUFG_FABRIC
Clock Management Functions
Overview
MMCMs
MMCM Primitive
Frequency Synthesis and Deskew
Without Deskew
With CLKFBOUT Deskew
Using the Deskew Logic
Using Fractional Divide
Jitter Filter
Limitations
VCO Operating Range
Minimum and Maximum Input Frequencies
Duty Cycle Programmability
Phase Shift
Static Phase Shift Mode Using Counters and VCO Phases (MMCM and XPLL) or DCO Phases (DPLL)
Dynamic Interpolated Fine Phase Shift in MMCM and XPLL (variable phase shift)
Dynamic Phase Shift Interface in the MMCM
Dynamic Reconfiguration Port (DRP)
MMCM Programming
MMCM Ports
MMCM Port Descriptions
MMCM Attributes
Counter Control
Detailed VCO and Output Counter Waveforms
Reference Clock Switching
MMCM Use Models
CLKIN Clock Network Deskew
MMCM with Internal Feedback - No Deskew
Zero Delay Buffer - CLKFBOUT Deskew
Deskew Logic - Additional Deskew Options
Use of the Deskew Logic
Functioning of Deskew
Safe Timing Clocking Topologies for MMCM and XPLL
Use Cases for Deskew
Phase Align Selected Clock Outputs of Two MMCMs
Phase Align Selected Clocks in Different ACAPs
Safe Timing Requirements for Multiple PLL and Clock Buffer Configuration
Fractional Divide Frequency Synthesis
MMCM/DPLL to MMCM/DPLL Connection
Spread-Spectrum Clock Generation
Spread-Spectrum Frequencies and Spread
Application Example
DPLLs
DPLL Primitive
Frequency Synthesis without Deskew
Frequency Synthesis with CLKFBOUT Deskew
Clock Network Deskew Using the Deskew Phase Detector and Phase Interpolator
Safe Timing Clocking Topologies for DPLL
Frequency Synthesis Using Integer Divide
Jitter Filter
Limitations
VCO Operating Range
Minimum and Maximum Input Frequencies
Phase Shift
Dynamic Phase Shift Interface in the DPLL
Counter Control
Detailed DCO and Output Counter Waveforms
DPLL Ports
DPLL Attributes
XPLLs
XPLL Primitive
Clock Network Deskew
Frequency Synthesis Using Integer Divide
Jitter Filter
Limitations
VCO Operating Range
Minimum and Maximum Input Frequencies
Duty Cycle Programmability
Phase Shift
Counter Control
Detailed DCO and Output Counter Waveforms
XPLL Ports
XPLL Port Descriptions
XPLL Attributes
XPLL Cascade
Clock Jitter Due to Memory Resource Activity
Noise on the Power Supply due to RAM Activity
Vivado Modeling of RAM Induced GCLK Jitter
Methods to Reduce URAA
System Setup and Conclusion
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

See Without Deskew.

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