External global user clocks must be brought into the Versal device on differential clock pin pairs called global clock (GC or GCIO) inputs. There are four GC pin pairs in each XPIO bank and two GC pin in every HDIO bank that have direct access to the global clock buffers, MMCMs, DPLLs, and XPLLs depending on their location on the device. The HDIO GC pins (HDGC pins) can be connected to DPLL directly. They can only be connected to MMCM and XPLL in XPIO through BUFGCE in HDIO. GC inputs provide dedicated, high-speed access to the internal global and regional clock resources. GC inputs use dedicated routing and must be used for clock inputs where the timing of various clocking features is imperative. General-purpose I/O with local interconnects must not be used for clock signals. Each XPIO bank is located in a single clock region and includes 54 I/O pins. Of the 54 I/O pins in each I/O bank in the I/O column, there are four global clock input pin pairs (a total of eight pins). Each global clock input:
- Can be connected to a differential or single-ended clock on the PCB
- Can be configured for any I/O standard, including differential I/O standards
- Has a P-side (master) and an N-side (slave)
- Can be cascaded to the MMCMs, DPLLs, and XPLLs in adjacent banks or through BUFGs to PLLs in non-adjacent banks
Single-ended clock inputs must be assigned to the P (master) side of the GC input pin pair. If a single-ended clock is connected to the P-side of a differential clock pin pair, the N-side cannot be used as another single-ended clock pin—it can only be used as an user I/O.
GC inputs are global clock input pins and can be used as regular I/O if not used as clocks. The global clock input pins can be configured as any single-ended or differential I/O standard. GC inputs can connect to the XPIO bank or adjacent to the same bank they reside in. The inputs can also connect to non-adjacent XPIO banks through BUFGs.
XCC inputs are clock capable input pins for XPHY related clocking and capable of accepting a strobe to capture data.
HDGC inputs are clock capable pins in a HDIO bank to source BUFGCE or DPLL.
For more information on how the above input pins are connected, refer to Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).