Limitations

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
AM003
Release Date
2022-05-24
Revision
1.4 English

XPLLs have some restrictions that must be adhered to. The major limitations are the VCO operation range, input frequency, and phase shift. In addition, there are connectivity limitations to other clocking elements (pins, GTs, and clock buffers). Cascading XPLLs can only occur through the clock routing network.