MMCM Attributes

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
AM003
Release Date
2022-05-24
Revision
1.4 English

The following table lists the attributes for the MMCME5 primitive.

Table 1. MMCM Attributes
Attribute Type Allowed Values Default Description
BANDWIDTH String

HIGH

LOW

OPTIMIZED

OPTIMIZED Specifies the MMCM programming algorithm affecting the jitter, phase margin, and other characteristics of the MMCM.
CLKOUT[0:6]_DIVIDE Decimal 2 to 511 2 Specifies the amount to divide the associated CLKOUT clock output if a different frequency is desired. This number, in combination with the CLKFBOUT_MULT_F and DIVCLK_DIVIDE values, determines the output frequency.
CLKOUT[0:6]_PHASE Real –360.000 to 360.000 0.000 Specifies the output phase relationship of the associated CLKOUT clock output in number of degrees offset (that is, 90 indicates a 90° or ¼ cycle offset phase offset while 180 indicates a 180° offset or ½ cycle phase offset). In static phase shift mode, the minimum phase step resolution (degrees) = (360/CLKOUT[0:6]_PHASE)/8
CLKOUT[0:6]_DUTY_CYCLE Real 0.001 to 0.999 0.5 Specifies the duty cycle of the associated CLKOUT clock output as a percentage (that is, 0.50 generates a 50% duty cycle).
CLKFBOUT_MULT Decimal 4 to 432 42 Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, determines the output frequency.
CLKFBOUT_FRACT Decimal 0 to 63 0 6-bit fractional M feedback divider in increments of 1/63. Generates a fraction of the CLKFBOUT_MULT value and adds it to CLKFBOUT_MULT.
DIVCLK_DIVIDE Decimal 1 to 123 1 Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD.
CLKFBOUT_PHASE Real –360.000 to 360.000 0.0 Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the MMCM.

REF_JITTER1

REF_JITTER2

Real 0.000 to 0.200 0.010 Allows specification of the expected jitter on the reference clock to better optimize MMCM performance. A bandwidth setting of OPTIMIZED attempts to choose the best parameter for input clocking when unknown. If known, the value provided should be specified in terms of the unit interval (UI) (the maximum peak-to-peak value) of the expected jitter on the input clock.
CLKIN1_PERIOD Real 0.000 to 100.000 0.000

Specifies the input period in ns to the MMCM CLKIN1 input.

Resolution is down to the ps. This information is mandatory and must be supplied.

CLKIN2_PERIOD Real 0.000 to 100.000 0.000

Specifies the input period in ns to the MMCM CLKIN2 input.

Resolution is down to the ps. This information is mandatory and must be supplied.

CLKOUTn_PHASE_CTRL[0:1] Binary 00 to 11 00

CLKOUT[0:6] counter variable fine phase shift or deskew select.

00: Interpolator is not controlled by either deskew or phase shift interface.

01: Interpolator is controlled by deskew1.

10: Interpolator is controlled by phase shift interface.

11: Interpolator is controlled by deskew2.

CLKOUTFB_PHASE_CTRL Binary 00 to 11 00

CLKFBOUT counter variable fine phase shift or deskew select.

00: Interpolator is not controlled by either deskew or phase shift interface.

01: Interpolator is controlled by deskew1.

10: Interpolator is controlled by phase shift interface.

11: Interpolator is controlled by deskew2.

DESKEW_DELAY1 Decimal 0 to 63 0 Value of the optional programmable delay in the deskew1 circuit.
DESKEW_DELAY2 Decimal 0 to 63 0 Value of the optional programmable delay in the deskew2 circuit.
DESKEW_DELAY_PATH1 String TRUE, FALSE FALSE Determines if the CLKIN1_DESKEW path or the CLKFB1_DESKEW path is selected for the optional programmable delay. TRUE = CLKFB1_DESKEW, FALSE = CLKIN1_DESKEW.
DESKEW_DELAY_PATH2 String TRUE, FALSE FALSE Determines if the CLKIN2_DESKEW path or the CLKFB2_DESKEW path is selected for the optional programmable delay. TRUE = CLKFB2_DESKEW, FALSE = CLKIN2_DESKEW.
DESKEW_DELAY_EN1 String FALSE, TRUE FALSE Set to TRUE to enable the optional programmable delay in the deskew circuit 1.
DESKEW_DELAY_EN2 String FALSE, TRUE FALSE Set to TRUE to enable the optional programmable delay in the deskew circuit 2.
COMPENSATION String

AUTO,

EXTERNAL,

INTERNAL,

BUF_IN

AUTO

Clock input compensation. Must be set to AUTO. Defines how the MMCM feedback is configured.

EXTERNAL: Indicates a network external to the device is being compensated.

INTERNAL: Indicates the MMCM is using its own internal feedback path so no delay is being compensated.

BUF_IN: Indicates that the configuration does not match with the other compensation modes. The CLKIN and CLKFBIN pins are aligned in a way that a delay in the feedback path is compensated with respect to CLKIN.

SS_EN String FALSE, TRUE FALSE Enables spread spectrum generation.
SS_MODE String

DOWN_LOW,

DOWN_HIGH,

CENTER_LOW,

CENTER_HIGH

CENTER_ HIGH Controls the spread spectrum frequency deviation and the spread type.
SS_MOD_PERIOD Decimal 4000–40000 10000 Specifies the spread spectrum modulation period (ns).
LOCK_WAIT String FALSE, TRUE FALSE Wait during the configuration startup for the MMCM to lock.
  1. The COMPENSATION attribute values are documented for informational purpose only. The Vivado® tools automatically select the appropriate compensation based on circuit topology. Do not manually select a compensation value, leave the attribute at the default value.
Tip: The port names generated by the clocking wizard can differ from the port names used on the primitive.