MMCM Port Descriptions

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
AM003
Release Date
2022-05-24
Revision
1.4 English
CLKIN1 – Primary Reference Clock Input
General clock input. Clocks can come from GC pins in adjacent XPIO banks, horizontal routing and vertical distribution. This input can be driven by all global clock buffers. However, if the source is a MBUFG type clock buffer, only output O1 can be used.
CLKIN2 – Secondary Clock Input
Secondary clock input to dynamically switch the MMCME5. Connectivity is identical to CLKIN1.
CLKFBIN – Feedback Clock Input
CLKFBIN must be connected either directly to the CLKFBOUT for internal feedback, or to the CLKFBOUT through a BUFG for clock buffer feedback matching or interconnect (not recommended). For clock alignment, the feedback path clock buffer type should match the forward clock buffer type.
Important: The internal compensation mode setting is determined by a direct connection (wire) from the CLKFBOUT to the CLKFBIN port in the source. However, synthesis optimizes this connection away such that the CLKFBOUT to CLKFBIN connection is removed from all subsequent representations in the Vivado® Design Suite. However, the INTERNAL compensation attribute attached to the MMCM/PLL indicates that the compensation is still internal to the MMCM/PLL.
CLKFBOUT – Dedicated MMCM Feedback Output
For possible configuration of CLKFBOUT. CLKFBOUT can also drive logic if the feedback path contains a clock buffer.
CLKINSEL – Clock Input Select
The CLKINSEL signal controls the state of the clock input multiplexers. High = CLKIN1, Low = CLKIN2. The MMCM must be held in RESET during clock switchover.
CLKOUT[6:0] – Output Clocks
These user-configurable clock outputs (CLKOUT0 through CLKOUT6) can be divided versions of the VCO phase outputs (user controllable) from 2 to 128. The input clock and output clocks can be phase aligned. For possible configurations, see MMCM Use Models. CLKFBOUT can be used to infer fractional mode for all CLKOUT outputs. The CLKOUT outputs can thus be used in fractional or non-fractional mode depending on the VCO mode. A static or dynamic phase shift can be applied to individual outputs. See the Phase Shift and Using Fractional Divide sections for more information.
CLKIN1_DESKEW
Primary clock input to the phase detector 1 block for deskewing clock network delays between two different CLKOUT networks. Use this pin to select one of the output clock that needs deskewing with respect to another output clock.
CLKFB1_DESKEW
Primary (feedback) clock input to the phase detector 1 block for deskewing clock network delays. Use this pin to select the output clock that needs deskewing with respect to the output clock selected for the CLKIN1_DESKEW.
CLKIN2_DESKEW
Secondary clock input to the phase detector 2 block for deskewing clock network delays between two different CLKOUT networks. Use this pin to select a second output clock that needs deskewing with respect to another output clock.
CLKFB2_DESKEW
Secondary (feedback) clock input to the phase detector 2 block for deskewing clock network delays. Use this pin to select the output clock that needs deskewing with respect to the output clock selected for the CLKIN2_DESKEW.
CLKINSTOPPED – Input Clock Status
This is a status pin indicating that the input clock has stopped. This signal is asserted within two CLKFBOUT clock cycles of clock stoppage. The signal is deasserted after the clock has restarted and LOCKED is achieved, or the clock is switched to the alternate clock input and the MMCM has re-locked.
CLKFBSTOPPED – Feedback Clock Status
This is a status pin indicating that the feedback clock has stopped. CLKFBSTOPPED is asserted within one clock cycle of clock stoppage. The signal is deasserted after the feedback clock has restarted and the MMCM has re-locked.
DADDR[6:0] – Dynamic Reconfiguration Address
The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for dynamic reconfiguration. The address value on this bus specifies the 16 configuration bits that are written or read with the next DCLK cycle. When not used, all bits must be assigned zeros.
DI[15:0] – Dynamic Reconfiguration Data Input
The dynamic reconfiguration data input (DI) bus provides reconfiguration data. The value of this bus is written to the configuration cells. The data is presented in the cycle that DEN and DWE are active. The data is captured in a shadow register and written at a later time. DRDY indicates when the DRP port is ready to accept another write. When not used, all bits must be set to zero.
DO[15:0] – Dynamic Reconfiguration Output Bus
The dynamic reconfiguration output bus provides MMCM data output when using dynamic reconfiguration. If DWE is inactive while DEN is active at the rising edge of DCLK, this bus holds the content of the configuration cells addressed by DADDR. The DO bus must be captured on the rising edge of DCLK when DRDY is active. The DO bus value is held until the next DRP operation.
DRDY – Dynamic Reconfiguration Ready
The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the MMCM’s dynamic reconfiguration feature. This signal indicates that a DEN/ DCLK operation has completed.
DWE – Dynamic Reconfiguration Write Enable
The dynamic reconfiguration write enable (DWE) input pin provides the write/read enable control signal to write the DI data into or read the DO data from the DADDR address. When not used, it must be tied Low.
DEN – Dynamic Reconfiguration Enable Strobe
The dynamic reconfiguration enable strobe (DEN) provides the enable control signal to access the dynamic reconfiguration feature and enables all DRP port operations. When the dynamic reconfiguration feature is not used, DEN must be tied Low.
DCLK – Dynamic Reconfiguration Reference Clock
The DCLK signal is the reference clock for the dynamic reconfiguration port. The rising edge of this signal is the timing reference for all other port signals. The setup time is specified in the Versal ACAP data sheets. There is no hold time requirement for the other input signals relative to the rising edge of the DCLK. The pin can be driven by an IBUF, IBUFG, BUFGCE, or BUFGCTRL. There are no dedicated connections to this clock input.
LOCKED, LOCKED1/2_DESKEW, and LOCKED_FB
LOCKED_FB is an output from the MMCM used to indicate when the MMCM has achieved phase and frequency alignment of the reference clock and the feedback clock at the input pins. Phase alignment is within a predefined window and frequency matching within a predefined PPM range. The MMCM automatically locks after power on; no extra reset is required. LOCKED_FB is deasserted within one PFD clock cycle if the input clock stops, the phase alignment is violated (for example, input clock phase shift), or the frequency has changed. The LOCKED1/2_DESKEW outputs indicate if the optional deskew circuit is used and has locked. The LOCKED output signals that the LOCKED_FB and LOCKED1/2_DESKEW circuits have achieved LOCK. Only unused LOCKED1/2_DESKEW circuits are considered for this AND function. The MMCM must be reset when LOCKED is deasserted. The clock outputs should not be used prior to the assertion of LOCKED.
PSCLK – Phase Shift Clock
This input pin provides the source clock for the dynamic phase shift interface. All other inputs are synchronous to the positive edge of this clock. The pin can be driven by an IBUF, IBUFG, BUFG, or BUFGCE. There are no dedicated connections to this clock input.
PSEN – Phase Shift Enable
A dynamic (variable) phase shift operation is initiated by synchronously asserting this signal. PSEN must be activated for one cycle of PSCLK. After initiating a phase shift, the phase is gradually shifted until a High pulse on PSDONE indicates that the operation is complete. There are no glitches or sporadic changes during the operation. From the start to the end of the operation, the phase is shifted in a continuous analog manner.
PSINCDEC – Phase Shift Increment/Decrement Control
This input signal synchronously indicates if the dynamic phase shift is an increment or decrement operation (positive or negative phase shift). PSENCDEC is asserted High for increment and Low for decrement. There is no phase shift overflow associated with the dynamic phase shift operation. If 360° or more are shifted, the phase wraps around, starting at the original phase.
PSDONE – Phase Shift Done
The phase shift done output signal is synchronous to the PSCLK. When the current phase shift operation is completed, the PSDONE signal is asserted for one clock cycle indicating that a new phase shift cycle can be initiated. If there is no new phase-shift cycle initiated, PSDONE continues to repeat a one-cycle High pulse every 32 PSCLK cycles.
RST – Asynchronous Reset Signal
The RST signal is an asynchronous reset for the MMCM. The MMCM is synchronously re-enabled when this signal is deasserted.
PWRDWN – Power Down
This signal powers down instantiated but currently unused MMCMs. This mode can be used to save power for temporarily inactive portions of the design and/or MMCMs that are not active in certain system configurations. No MMCM power is consumed in this mode.