Navigating Content by Design Process

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
AM003
Release Date
2022-05-24
Revision
1.4 English

Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All Versal® ACAP design process Design Hubs and the Design Flow Assistant materials can be found on the Xilinx.com website. This document covers the following design processes:

System and Solution Planning
Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine. Topics in this document that apply to this design process include:
Hardware, IP, and Platform Development​
Creating the PL IP blocks for the hardware platform, creating PL kernels, functional simulation, and evaluating the Vivado® timing, resource use, and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include:
  • Clock Buffer Resources: describes the set of clock buffers that drive the routing and distribution resources across the entire device.
  • Clock Management Functions: describes the clock functions to generate clocking for specific and general purposed tasks in ACAPs.