Overview

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
AM003
Release Date
2022-05-24
Revision
1.4 English
In VersalĀ® ACAPs, clock management includes:
  • MMCM (analog PLL with extended functions for general purpose clocking usage)
  • XPLL (analog PLL to support XPHY and provide additional general purpose clocking usage)
  • DPLL (MMCM lite version of PLL)

All three clock functions are designed to generate clocking for specific and general purpose tasks in Versal ACAP. The purpose of the MMCM is to generate clocks of different frequencies for various general purpose applications. The other two are designed to fill the needs and special requirements of certain blocks like XPIO while maintaining some secondary, general purpose functionality by supporting a limited subset of the MMCM capabilities that can be used for general clocking purposes.

The following figure provides a more detailed view of the location of clock management elements, MMCM and PLL, in the Versal architecture. Refer to Clock Management MMCM, XPLL, and DPLL for a high-level view of where clock management components are placed within the Versal architecture.

Unlike all previous architectures, Versal ACAP is actually a combination of dedicated or specialized hardware components along with standard programmable logic. Clocking management and structures are no longer formatted within a regular structure; they are only placed where required.

The structure of a device is still divided into clock regions (although not in rigid blocks) which segment the device into functional areas: configurable logic, memory, hard IP, and signal and clock routing. Segmentation in the clock regions makes it possible to model devices to target specified needs and/or markets.

Clock regions with clock management functions are available in a XCVC1902 device. These appear in different compositions in all other Versal ACAPs.

Top-left and right-half clock region with high-density I/O bank
  • Half-clock region in this device featuring a high-density I/O bank. This is the top side of a clock region because that includes all clock buffers and the horizontal clock spine.
  • A DPLL and clock buffers (24x BUFGT_GT and 41x BUFGT_GT_SYNC) are available to serve the high speed serial GT (GTY, GTH, ...) components and their programmable logic.
  • A DPLL and clock buffers (4x BUFGCE) is available to serve all clock needs of the high-density I/O and required programmable logic. The horizontal clock spine with BUFDIV_LEAF buffers runs from left to right and vice versa over the device.
    Figure 1. Top Left and Right Clock Regions

Left and right clock region with hard-IP blocks
  • In this case, the clock region is used full and half-sized. The top side of the clock region, containing all clock buffers and horizontal clock spine, is used when half a clock region is implemented. On the left side, on the top of the CPM processor, a top half clock region is used.
  • These clock regions are where the hard-IP blocks are: PCIe, DCMAC, ILKN, and others.
  • A DPLL and clock buffers (24x BUFGT_GT and 41x BUFGT_GT_SYNC) are available to serve the high-speed serial GT (GTY, GTH, ...), hard-IP blocks components and their programmable logic. The horizontal clock spine with BUFDIV_LEAF buffers runs from left to right and vice versa over the device.
    Figure 2. Middle Left and Right Clock Regions

Middle buried clock regions
  • Clock regions where a vertical NoC spine passes are regions where in the top side of that clock region 24 BUFG_FABRIC clock buffers are available.
  • All other clock regions only have the horizontal clock spine in the top side of the region.
  • The clock region next to the processor subsystem contain as set of 24 BUFG-PS clock buffers.
Bottom clock regions
  • These are clock regions housing dedicated memory controller IP and high-speed select I/O components.
  • The clock regions are: DPLL, MMCM, a dual-XPLL supplemented with 24 BUFGCE, 8 BUFGCTRL, and 4 BUFGCE_DIV.
    Figure 3. Bottom Clock Regions