- MMCME5
- A mixed-mode clock manager (MMCM) is a general purpose phase-locked loop
(PLL) used for all-purpose clock generation as well as for deskewing
applications. In
Versal®
ACAPs, the
functionalities and capabilities of MMCM are broadly similar to that of
UltraScale+™
devices. For more information,
see MMCM Primitive.
- XPLL
- XPLL is a PLL that is situated in between the XPIO banks. It provides clock
output to both, the XPHY logic and the programmable logic of the ACAP. It can
also be used for deskewing applications. In Versal devices, the functionalities and capabilities of XPLL are
broadly similar to that of PLL. For more information, see XPLL Primitive.
- DPLL
- DPLL is a PLL that is located next high-density I/O (HDIO) banks, and the GT
clocking column. It provides clock output to the programmable logic of the ACAP.
It can also be used for deskewing applications. The functionalities and
capabilities of DPLL are similar to that of MMCM and XPLL. Refer to DPLL Primitive for more information.
- Clock Buffer Primitives
- The clock buffers in Versal devices are
similar to the clock buffers in UltraScale+ devices including:
- BUFGCTRL block for glitchless clock muxing and
gating
- BUFGCE block for glitchless clock gating
- BUFGCE_DIV block for clock division
- BUFG_GT block for clock division of GT clocks
- BUFG_PS block for PS/PMC
For more information, see BUFGCTRL Clock Buffer Primitives.