Safe Timing Requirements for Multiple PLL and Clock Buffer Configuration

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
AM003
Release Date
2022-05-24
Revision
1.4 English

This section describes the requirements for safe timing that apply between two CLKOUTs of multiple PLLs and clock buffers in various configurations. The setup is not dependent on any type of deskew.

Parallel PLLs

Refer to the figure below for this configuration.

  • The PLLs must have a common input clock and the input divide (D) must be set to 1.
  • The PLLs must have the same multiply (M) values.
  • The ratio M/O (O= CLKOUTx output divide value) must be an integer. Any clock of the PLL that follows this integer rule can be safely timed with any other clock of the parallel PLL.
  • When parallel PLLs are in digital deskew mode, i.e., CLKOUTx_PHASE_CTRL = 01 or 11, see Safe Timing Clocking Topologies for MMCM and XPLL for information on when it is safe to time between CLKOUTs provided the conditions in this section are also met.
Figure 1. Parallel PLLs

Cascaded PLLs

Refer to the figure below for this clocking topology

  • M/(D*O) must be an integer, where M, D, and O are from the cascaded PLL.
  • M and D of the leading PLL only impact the safe timing requirements from CLKIN to CLKOUTs, similar to the single PLL case.
Figure 2. Cascaded PLLs

Parallel BUFGCE_DIVs

The requirements to enable safe timing between parallel BUFGCE_DIVs are as follows:

  • All BUFGCE_DIVs must have the same input clock or driven by clocks with a known phase relationship.
  • When one of the two following conditions is met:
    • The dividers within the BUFGCE_DIV are deterministically enabled, that is, the CE inputs between the blocks can be timed or are driven by the same logic.
    • The input clocks stop for all the BUFGCE_DIVs when the BUFGCE_DIVs are enabled.
  • When CE_TYPE=HARDSYNC, it is never safe to time between outputs of parallel buffers and between input and output clocks of the BUFGCE*.

Combination of PLL and BUFGCE_DIV

Refer to the figures in this section for this topology. In case 1, both the PLL and BUFGCE_DIV have to be driven by the same input clock. BUFGCE_DIV needs to be deterministically enabled using an output clock from the PLL, that is, the CE pin of the BUFGCE_DIV must be driven by logic clocked by CLKOUTx of the PLL. Case 2 is similar to a regular topology and the standard PLL CLKIN to CLKOUT restrictions apply.

Figure 3. BUFGCE_DIV Feeding to CLKIN of PLL