Using Fractional Divide

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
AM003
Release Date
2022-05-24
Revision
1.4 English

Versal ACAPs support fractional (non-integer) divides in the feedback path resulting in a fractional VCO frequency. The method of fractional divide from UltraScale™ devices has been replaced with a sigma-delta module (SDM) based fractional mode. The MMCM now supports fractional divide ratios with a 6-bit resolution which is far finer than the 0.125 resolution supported in the UltraScale devices. The CLKOUT0 output counter does no longer have a fractional capability. The MMCM supports a 6-bit fractional modulus which enables it to synthesize frequency in a much finer granularity.

To use the integer mode, fractional SDM must be disabled. The fractional modulus of the MMCM feedback divide is 6-bit wide, hence the frequency can be set to any fractional value equal to n/64, where n = 1, 2, …, 63, or expressed differently 1/(26) 2/(26), ... , 63/(26). When in fractional mode, it is advised to choose M value that generates the highest possible VCO frequency within the VCO operating range to achieve the best possible jitter performance. However, only the output frequency and input jitter will impact the clock uncertainty reported in the Versal ACAP and the Vivado tools will not model the improvement. The Clocking Wizard automatically implements all the necessary settings when fractional divide is used.