Using the Deskew Logic

Versal ACAP Clocking Resources Architecture Manual (AM003)

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1.4 English

In addition to the normal deskew options, internal feedback, or clock network delay feedback using CLKFBOUT, deskew logic features are also available in the MMCM and PLL of Versal ACAPs. MMCM and XPLL have two deskew logic units while a DPLL has one. A deskew logic unit consists of CLKIN_DESKEW and CLKFB_DESKEW pins along with a deskew phase detector (PD) and a set of shared phase interpolators (PI). Clock network deskew can be achieved using a deskew phase detector (PD) and with the limitation that the PI associated with the feedback counter cannot be used for deskewing using the deskew PD. An MMCM/XPLL can receive four additional clock inputs (CLKIN1_DESKEW/CLKIN2_DESKEW and CLKFB1_DESKEW/CLKFB2_DESKEW) to help eliminate skew between two pairs of clock networks while with two additional inputs (CLKIN1_DESKEW and CLKFB1_DESKEW) a DPLL can only deskew one clock network. Note that both the CLKIN_DESKEW and CLKFB_DESKEW clock network pairs must have the same frequency. For more information about requirements on the sets of clock inputs, see Functioning of Deskew. The duty cycles of the two inputs are not required to be the same provided that they are within specification and the phases can be different. Each of the seven output counters and the feedback counter receive input from their associated PI. The PIs can be controlled by either one of the two deskew PDs, the phase shift interface, or by neither. It is possible to deskew two different pairs of clock networks using this system. There is also an option to add programmable delay to either of the two clock inputs of a deskew PD. The Vivado tools calculate the proper delay values for fine tuning the skew compensation. However, it is also possible to manually enable or disable the delays, adjust the delay line settings, and select the multiplexer CLKIN_DESKEW or CLKFB_DESKEW inputs using the attributes DESKEW_DELAY_EN, DESKEW_DELAY, and DESKEW_DELAY_PATH. The analog external feedback (CLKFBOUT) has limitations on the amount of delay that can be added to the external feedback path before making the MMCM unstable.

Figure 1. MMCM Clock Network Deskew Using Deskew Logic