Vivado Modeling of RAM Induced GCLK Jitter

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
AM003
Release Date
2022-05-24
Revision
1.4 English

Vivado tools model a baseline GCLK jitter. This baseline jitter is then increased based on the RAM activity defined for the top-level (current_design) object. Internally Vivado tools use a property that describes the RAM activity called RAM_AVERAGE_ACTIVITY (RAA).

A simple definition for this parameter is that it is equal to the average RAM frequency for all the RAMs on the part in MHz. This simple definition captures both the frequency of the RAMs and the percentage of RAMs that are used on the part.

For the 2021.2 release, the Vivado tools perform a pessimistic estimate of RAM activity for flat designs. The value computed is applied to the RAM_AVERAGE_ACTIVITY property on the top-level [current_design] object.

You can override the Vivado tools default by setting the USER_RAM_AVERAGE_ACTIVITY (URAA) property. The Vivado tools command is:

set_property USER_RAM_AVERAGE_ACTIVITY ### [current_design]

Calculation of the URAA is described in the following sections.

The Vivado tools cannot determine how many RAMs can simultaneously be enabled or disabled and how frequently that can occur. Because of this, the Vivado tools assume a worst-case condition in which all RAMs are simultaneously enabled and disabled at a minimum rate of 22 MHz. These assumptions are further discussed in Methods to Reduce URAA.

Manual Calculation of URAA

URAA can be manually calculated for a design using the following formula. This calculated value can then be set on the URAA parameter which will override the Vivado tools default.

URAA = Sum of the RAM frequencies (SumRAMF) / Total RAMs.

where,

SumRAMF = 0.5 * SumF(BRAM36) + 0.25 * SumF(BRAM18) + SumF(URAM)

where,

SumF(BRAM36) = sum of the frequencies for each BRAM36 site
SumF(BRAM18) = sum of the frequencies for each BRAM18 site
SumF(URAM) = sum of the frequencies for each URAM site
TotalRAMs = 0.5 * BRAM36 sites + URAM sites
SumF(BRAM18) = sum of the frequencies for each BRAM18 site
SumF(URAM) = sum of the frequencies for each URAM site
TotalRAMs = 0.5 * BRAM36 sites + URAM sites
Note: Only the BRAM36 sites are counted in this formula because each BRAM36 site contains two BRAM18 sites.

The following commands can be used within Vivado tools to report out the total number of BRAM36 and URAM sites.

llength [get_sites RAMB36*]
llength [get_sites URAM*]

Following is an example of the calculation for the total number of RAMs for the xcvc1902-viva1596-1LP-e-S part.

Table 1. Example of Total Number of RAMs calculation
Part BRAM36 URAM Total Number of RAMs for URAA Calculation
xcvc1902-viva1596-1LP-e-S 967 463 946.5

Script-Based Calculation of URAA

A script is available that can be run at the top-level of the design to calculate the URAA. The script performs the calculations in the previous section and generates an XDC file specifying the URAA value. The script must be run on a top-level final and completed design. If any changes are made which involve RAMs used (number of instances, state of enable pins, etc.), the script needs to be rerun. The XDC file can then be used as a constraints source in Vivado tools.

Any RAM with their enable tied high or low by definition has a switching rate of 0 MHz. RAMs that have their enable tied to an active signal will be treated as having a frequency of the highest clock frequency arriving at the RAM based on the design timing constraints.

This script does not account for the impact of clock gating. If clock gating is used within the design the user will need to manually calculate the RAA value. Also, certain pessimistic assumptions have been made for this calculation. For more information, see Methods to Reduce URAA.

To access the script, see Xilinx Answer Record 76369.