XPLL Ports

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
AM003
Release Date
2022-05-24
Revision
1.4 English

The XPLL has a set of ports specifically for the RIU XPHY interface signals (the XPLL-RIU interface). These pins can be directly connected to control the interface. For available pins see the tables below.

Table 1. XPLL Ports
Port Name I/O Description
CLKIN Input General clock input.
RST Input Asynchronous reset signal. The RST signal is an asynchronous reset for the XPLL. The XPLL synchronously re-enables itself when this signal is released (that is, XPLL re-enabled). A reset is required when the input clock conditions change (for example, frequency).
PWRDWN Input Powers down instantiated but unused PLLs.
CLKOUT[0:3] Output User configurable clock outputs (0 through 3) that can be divided versions of the VCO phase outputs (user controllable) from 2 to 128. The output clocks are phase aligned to each other (unless phase shifted).
CLKOUTPHYEN Input Asynchronous enable of the XPHY clock.
CLKOUTPHY Output Dedicated XPHY clock.
CLKIN1_DESKEW Input Primary clock input to the phase detector 1 block for deskewing clock network delays between two different CLKOUT networks.
CLKFB1_DESKEW Input Secondary (feedback) clock input to the phase detector 1 block for deskewing clock network delays.
CLKIN2_DESKEW Input Primary clock input to the phase detector 2 block for deskewing clock network delays between two different CLKOUT networks.
CLKFB2_DESKEW Input Secondary (feedback) clock input to the phase detector2 block for deskewing clock network delays.
LOCKED Output The LOCKED signal indicates that all functions requiring a LOCKED signal for the XPLL to operate properly have LOCKED. This LOCKED signal is therefore an AND function of LOCKED_FB and both LOCKED1/2_DESKEWs, if used.
LOCKED_FB Output An output from the XPLL that indicates when the XPLL has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The XPLL automatically locks after power on. No extra reset is required. LOCKED is deasserted if the input clock stops or the phase alignment is violated (for example, input clock phase shift). The XPLL must be reset after LOCKED is deasserted.
LOCKED1/2_DESKEW Output Indicates if the deskew circuit is locked. Applies only to the deskew circuits used in the design. Ignore these outputs for unused deskew circuits.
DO[15:0] Output The dynamic reconfiguration output bus provides XPLL data output when using dynamic reconfiguration.
DI[15:0] Input The dynamic reconfiguration data input (DI) bus provides reconfiguration data. When not used, all bits must be set to zero.
DADDR[6:0] Input The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros.
DRDY Output The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the XPLL’s dynamic reconfiguration feature.
DWE Input The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it must be tied Low.
DEN Input The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low.
DCLK Input The DCLK signal is the reference clock for the dynamic reconfiguration port.
PSCLK Input Dynamic phase shift clock.
PSEN Input Dynamic phase shift enable.
PSINCDEC Input Dynamic phase shift increment/decrement control.
PSDONE Output Dynamic phase shift done.
RIU_CLK Output DMC XPHY RIU interface clock.
RIU_ADDR<7:0> Input DMC XPHY RIU interface address.
RIU_WR_DATA<15:0> Output DMC XPHY RIU interface write data.
RIU_RD_DATA<15:0> Input DMC XPHY RIU interface read data.
RIU_WR_EN Input DMC XPHY RIU interface write Enable.
RIU_NIBBLE_SEL Input DMC XPHY RIU interface XPHY nibble select.
RIU_VALID Output DMC XPHY RIU interface valid.
  1. All control and status signals except PSINCDEC are active-High.
Tip: The port names generated by the clocking wizard can differ from the port names used on the primitive.