The XPLL is a mixed-signal block designed to support clock network deskew, frequency synthesis, and jitter reduction. The primary function of the XPLL is to support the clocking needs of the memory interface. It also provides clocks to the programmable logic for various general purpose applications. There are two PLLs per XPIO bank that provide clocking to the XPHY logic and XPIO. In addition, they can be used as general purpose frequency synthesizers for a wide range of frequencies, serve as jitter filters, and provide phase shift capabilities as well as duty cycle programming. The basic functionality and operating functions are mostly identical to the description in MMCM section. The XPLLs differ from the MMCM in number of outputs (4), multipliers, and output dividers which have a lesser value range. However, the XPLL has special hardware features and connections to specifically support high performance direct clocking of the XPHY. XPLLs do not have fractional clock generation.
Figure 1. XPLL Block Diagram