Zero Delay Buffer - CLKFBOUT Deskew

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
AM003
Release Date
2022-05-24
Revision
1.4 English

The MMCM can also be used to generate a zero delay buffer clock. A zero delay buffer can be useful for applications where there is a single clock signal fanout to multiple destinations with a low skew between them. This configuration is shown in the following figure.

In this case, the feedback signal drives off chip and the board trace feedback is designed to match the trace to the external components. It is assumed in this configuration that the clock edges are aligned at the input of the Versal ACAP and the input of the external component. The input clock buffers for CLKIN and CLKFBIN must be in the same bank.

Figure 1. Zero Delay Buffer - CLKFBOUT Deskew

In some cases, precise alignment cannot occur because of the difference in loading between the input capacitance of the external component and the feedback path capacitance of the Versal device. For example, the external components can have an input capacitance of 1 pF to 4 pF while the part has an input capacitance as specified in the Versal ACAP data sheets. There is a difference in the signal slope, which is basically skew. Designers should be aware of this effect to help ensure timing.