The DSP58 input data ports support many common algorithms. DSP58 has four direct input data ports labeled A, B, C, and D. The A data port is 34 bits wide, the B data port is 24 bits wide, the C data port is 58 bits wide, and the preadder D data port is 27 bits wide.
The 27bit A (A[26:0]) and 24bit B ports supply input data to the 27bit by 24bit, two’s complement multiplier. With the independent C port, each DSP58 is capable of multiplyadd, multiplysubtract, and multiplyround operations.
Concatenated A and B ports (A:B) bypass the multiplier and feed the X multiplexer input. The 34bit A input port forms the upper 34 bits of A:B concatenated datapath, and the 24bit B input port forms the lower 24 bits of the A:B datapath. The A:B datapath, together with the C input port, enables each DSP58 to implement a full 58bit adder/subtracter provided the multiplier is not used, which is achieved by setting USE_MULT to NONE.
Each DSP58 also has two cascaded input datapaths (ACIN and BCIN) that provide a cascaded input stream between adjacent DSP58s in the same column. The cascaded path is 34 bits wide for the A input and 24 bits wide for the B input. Applications benefiting from this feature include FIR filters, complex multiplication (larger than 18 × 18), multiprecision multiplication, and complex MACCs (larger than 18 × 18).
The A and B input port and the ACIN and BCIN cascade port can have 0, 1, or 2 pipeline stages in its datapath. The dual A, D, and preadder port logic is shown in Figure 1. The dual B register port logic is shown in Figure 2. The different pipestages are set using attributes. Attributes AREG and BREG are used to select the number of pipeline stages for A and B direct inputs to the X multiplexer to the ALU, and INMODE[0] can dynamically change the number of pipeline stages to the multiplier. Attributes ACASCREG and BCASCREG select the number of pipeline stages in the ACOUT and BCOUT cascade datapaths. The allowed attribute settings are shown in Table 1. Multiplexers controlled by configuration bits select flow through paths, optional registers, or cascaded inputs. The data port registers allow users to typically trade off increased clock frequency (that is, higher performance) versus data latency.
The following table shows the encoding for the INMODE[4:0] dynamic control bits and AMULTSEL, BMULTSEL, and PREADDINSEL static control bits.
These bits select the functionality of the preadder, the A, B, and D input registers. AMULTSEL and/or BMULTSEL must be set to AD to enable the preadder functions described in the table. Additionally, a new dynamic control port called NEGATE, is used to conditionally negate the multiplier product.
In summary, the INMODE dynamic control signals along with AMULTSEL, BMULTSEL, and PREADDINSEL static attributes control the preadder functionality and A, B, and D register bus multiplexers that precede the multiplier, as well as the multiplier product negation controlled by NEGATE control signals that have an effect on the multiplier. The DSP58 supports twodeep A or B sourcing the preadder as well as a preadder squaring function.
NEGATE[0]^{ 4 }  INMODE[4]  INMODE[3]  INMODE[2]  INMODE[1]  INMODE[1]A^{ 1 }  INMODE[1]B^{ 1 }  INMODE[0]  PREADDINSEL  BMULTSEL  AMULTSEL  Multiplier A Port  Multiplier B Port^{ 3 }  PreAdder/Multiplier Function 

0/1  0/1  0  0  0  0  0  0/1  A/B  B  A  A2/A1  B2/B1  ±A[26:0] * B[23:0] 
0/1  0/1  0/1  1  0  0  0  0/1  A  B  AD  D ± A2/A1^{ 2 }  B2/B1  ±(D[25:0] ± A[25:0]) * B[23:0] 
0/1  0/1  0  0  1  1  0  X  A  B  A  Zero  B2/B1  Zero 
0/1  0/1  0  0  1  0  1  X  B  B  A  A2/A1  Zero  Zero 
0/1  X  0/1  1  0  0  0  0/1  A  AD  AD  D ± A2/A1^{ 2 }  D ± A2/A1^{ 2 }  ±(D[22:0] ± A[22:0])^{ 2 } 
0/1  X  0  1  1  1  0  X  A  AD  AD  D  D  ±D[23:0]^{ 2 } 
0/1  X  0/1  0  0  0  0  0/1  A  AD  AD  ± A2/A1  ± A2/A1  ±A[23:0]^{ 2 } 
0/1  X  0/1  1  0  0  0  0/1  A  AD  A  A2/A1  D ± A2/A1^{ 2 }  ±(D[22:0] ± A[22:0]) * A[22:0] 
0/1  0/1  0/1  1  0  0  0  0/1  B  AD  A  A2/A1  D ± B2/B1^{ 2 }  ±(D[22:0] ± B[22:0]) * A[26:0] 
0/1  X  0  1  1  0  1  0/1  B  AD  A  A2/A1  D  ±D[23:0] * A[26:0] 
0/1  0/1  0/1  1  0  0  0  0/1  B  AD  AD  D ± B2/B1^{ 2 }  D ± B2/B1^{ 2 }  ±(D[22:0] ± B[22:0])^{ 2 } 
0/1  0/1  0/1  0  0  0  0  0/1  B  AD  AD  ± B2/B1  ± B2/B1  ±B[23:0]^{ 2 } 
0/1  0/1  0/1  1  0  0  0  0/1  B  B  AD  D ± B2/B1^{ 2 }  B2/B1  ±(D[25:0] ± B[22:0]) * B[22:0] 
A[26]  0  X  0  0  0  0  0  X  B  A  A  B = 1  A[26:0] 
B[23]  0  X  0  0  0  0  0  X  B  A  A = 1  B  B[23:0] 
D[26]  0/1  0  1  1  1  0  0/1  A  B  AD  D + Zerp  B = 1  D[26:0] 

INMODE[0] selects between A1 (INMODE[0] = 1) and the A2 MUX controlled by AREG (INMODE[0] = 0).
INMODE[1] can be used to gate the A or B datapath to use the preadder to create a 2:1 bus multiplexer along with the INMODE[2] control signal.
When INMODE[2] = 0, the D input to the preadder is 0. INMODE[1] and INMODE[2] enable multiplexing between the D register and the A or B registers, without having to use resets to force them to zero. For information on how to configure the preadder as a 2:1 multiplexer, see PreAdder Block Applications.
INMODE[3] provides preadder subtract control, where INMODE[3] = 1 indicates subtract and INMODE[3] = 0 indicates add of A or B to D. When D is gated off, this dynamic inversion can provide the absolute value of A or B.
INMODE[4] selects between B1 (INMODE[4] = 1) and the B2 MUX controlled by BREG (INMODE[4] = 0).
The 58bit C port is used as a general input to the W, Y, and Z multiplexers to perform add, subtract, fourinput add/subtract, and logic functions. The C input is also connected to the pattern detector and can be used to support rounding function implementations. The C port logic is shown in the following figure. The CREG attribute selects the number of pipestages for the C input datapath.