In typical direct form FIR filters, an input stream of samples is presented to one input of the multipliers in the DSP58s. The coefficients supply the other input to the multipliers. An adder tree is used to combine the outputs from many multipliers as shown in the following figure.
In the traditional approach, the adders in the programmable logic (PL) are usually the performance bottleneck. The number of adders needed and the associated routing depends on the size of the filter. The depth of the adder tree scales as the log2 of the number of taps in the filter. Using the adder tree structure shown in the figure above could also increase the cost, logic resources, and power.