The complex FIR equation is represented as follows.

where:

the ith complex coefficient is:

the complex input sample is:

the complex output sample is:

The following figure is a simplified block diagram of the filter design.

- ‘x’ corresponds to complex input and maps to B_RE/B_IM ports.
- ‘a’ corresponds to complex coefficient and maps to A_RE/A_IM ports. The design is provided as an inference example therefore, the inputs can be swapped depending on the tool choice.
- ‘c’ corresponds to cascade path from PCOUT_RE/IM ports of one DSP58 to PCIN_RE/IM ports of the next.

In the DSPCPLX configuration, each tap in the complex FIR filter is
comprised of two DSP58s (provided they are 18 bits wide complex numbers or fewer)
configured as a complex multiply-add unit. The PCOUT/PCIN ports (real and imaginary
portion) are used to cascade in the output of the final adder from the previous tap to
the next (shown as c_{Q} and c_{I} in
the diagram, except the first tap). The z^{-1} blocks represent
delay stages for pipelining.

Coding examples are available in Language Templates with the Vivado® Integrated Design Environment (IDE) 2020.2 version.