Generation of Complex Conjugates for Multiplication
The 18bit complex multiplier that straddles two backtoback DSP58s produces a complex product. See the complex multiplier example in DSP58 Applications for details on generation of complex conjugates and coding example.
OPMODE Control
As shown in the Right DSP58 and Left DSP58 figures in Basic Function and Complex Adder, OPMODE controls the behavior of the X,Y,Z,W multiplexers (same as DSP58, which constitutes the DSPCPLX basic block. (See W, X, Y, and Z Multiplexers for details.)
A more detailed explanation on how OPMODE_RE and OPMODE_IM are used to determine the final result follows. The examples consider CONJUGATE_RE=CONJUGATE_IM=1’b0. See the table in 18 × 18 Complex Multiply using DSPCPLX for more information on the effect of other values assigned to these signals.
 X,Y Multiplexers: OPMODE_RE[3:0] = OPMODE_IM[3:0] = 4'b0101.
 This configuration selects the multiplier output in both Real and Imaginary parts to go through the X and Y multiplexers to feed the final ALU. This selection allows the required complex multiplication, therefor the X and Y multiplexer should not be used for other purposes. The only exception is the MACC extension application. The MACC extension equation is covered in the following “Z Multiplexer” section. Additional information is provided in MACC Extension.
Complex Multiplication Equation  OPMODE_RE  OPMODE_IM 

P_{RE} + j P_{IM} = (A_{RE} + j A_{IM } ) (B_{RE} + j B_{IM } ) = (A_{RE }× B_{RE } A_{IM} × B_{IM } ) + j (A_{RE} × B_{IM} + A_{IM} × B_{RE } ) 
9’b00_000_01_01  9’b00_000_01_01 
 Z Multiplexer: PMODE_RE[6:4] = OPMODE_IM[6:4] = Kz.
 The value assigned to these control signals determine the Z multiplexer output that are forwarded to the ALU. "DSPCPLX Lower" and "DSPCPLX Upper" in the table below represent a DSP cascade configuration in the complex mode (see the figure at the end of this subsection).
Complex Multiplication Equation with Addition Equation  OPMODE_RE  OPMODE_IM  

_{DSPCPLX Lower} 
P_{LRE } + j P_{LIM } = ( A_{LRE } + j A_{LIM } ) × ( B_{LRE } + j B_{LIM } ) ( A_{LRE } × B_{LRE } A_{LIM }× B_{LIM } ) + j ( A_{LRE } × B_{LIM }+ A_{LIM } × B_{LRE } ) 
9’b00_000_01_01  9’b00_000_01_01 
_{DSPCPLX Upper} 
P_{URE } + j P_{UIM } = ( P_{URE } + j P_{UIM } + ( ( A_{URE } + j A_{UIM } ) × ( B_{URE } + j B_{UIM } ) ) = ( ( A_{LRE } × B_{LRE } + A_{URE } × B_{URE } )  ( A_{LIM } × B_{LIM } + A_{UIM } × B_{UIM } ) ) + j ( ( A_{LRE } × B_{LIM } + A_{URE } × B_{UIM } + A_{LIM } × B_{LRE } + A_{UIM } × B_{URE } ) ) 
9’b00_001_01_01  9’b00_001_01_01 
Kz: 2'b11  RND: Addition to the result of the current DSPCPLX; (DSP Upper) instance of a downstream DSPCPLX (DSP Lower) 
Complex Multiplication with Accumulation Equation  OPMODE_RE  OPMODE_IM 

P_{RE} + j P_{IM} = ( P*_{RE} + j P*_{IM} ) + ( ( A_{RE} + j A_{IM } ) × ( B_{RE} + j B_{IM } ) ) = ( P*_{RE} + ( A_{RE} × B_{RE}  A_{IM }× B_{IM} _{ } ) ) + j ( P*_{IM} + ( A_{RE} × B_{IM} + A_{IM }× B_{RE} _{ } ) ) * = value stored in the P_{RE} and P_{IM} registers 
9’b00_010_01_01  9’b00_010_01_01 
Kz: 3’b010  P: Output accumulation acting independently on the Real and Imaginary side. Requires PREG=1. 
Complex Multiplication With Addition Equation  OPMODE_RE  OPMODE_IM 

P_{RE} + j P_{IM} = ( C_{RE} + j C_{IM} ) + ( ( A_{RE} + j A_{IM } ) × ( B_{RE} + j B_{IM } ) ) = ( C_{RE} + ( A_{RE} × B_{RE}  A_{IM }× B_{IM} _{ } ) ) + j ( C_{IM} + ( A_{RE} × B_{IM} + A_{IM }× B_{RE} _{ } ) ) 
9’b00_011_01_01  9’b00_011_01_01 
Kz: 3’b011  C: Additional complex number added independently on the Real and Imaginary side 
MACC Extension Equation  OPMODE_RE  OPMODE_IM 

P_{RE} + j P_{IM} = ( P*_{RE} + j P*_{IM} ) + ( ( A_{RE} + j A_{IM } ) × ( B_{RE} + j B_{IM } ) ) = ( P*_{RE} + ( A_{RE} × B_{RE}  A_{IM }× B_{IM} _{ } ) ) + j ( P*_{IM} + ( A_{RE} × B_{IM} + A_{IM }× B_{RE} _{ } ) ) * = value stored in the P_{RE} and P_{IM} registers 
_{DSPCPLX Lower} 9’b00_010_01_01 _{DSPCPLX Upper} 9’b00_100_01_01 
_{DSPCPLX Lower} 9’b00_010_01_01 _{DSPCPLX Upper} 9’b00_100_01_01 
Kz: 3’b100  P: Output accumulation acting
independently on the Real and Imaginary side. In a DSPCPLX cascade
designed for MACC extension, the upper DSPCPLX must have:

See MACC Extension for details on MACC operation usage.
 W Multiplexer: OPMODE_RE[8:7] = OPMODE_IM[8:7] = Kw
 The value assigned to these control signals determine the Z multiplexer output that is forwarded to the ALU.
Complex Multiplication with Accumulation Equation  OPMODE_RE  OPMODE_IM 

P_{RE} + j P_{IM} = ( P*_{RE} + j P*_{IM} ) + ( ( A_{RE} + j A_{IM } ) × ( B_{RE} + j B_{IM } ) ) = ( P*_{RE} + ( A_{RE} × B_{RE}  A_{IM }× B_{IM} _{ } ) ) + j ( P*_{IM} + ( A_{RE} × B_{IM} + A_{IM }× B_{RE} _{ } ) ) * = value stored in the P_{RE} and P_{IM} registers 
9’b01_000_01_01  9’b01_000_01_01 
Kw: 2’b01  P: Output accumulation acting independently on the Real and Imaginary side. Requires PREG=1. 
Complex Multiplication with Addition Equation  OPMODE_RE  OPMODE_IM 

P_{RE} + j P_{IM} = ( C_{RE} + j C_{IM} ) + ( ( A_{RE} + j A_{IM } ) × ( B_{RE} + j B_{IM } ) ) = ( C_{RE} + ( A_{RE} × B_{RE}  A_{IM }× B_{IM} _{ } ) ) + j ( C_{IM} + ( A_{RE} × B_{IM} + A_{IM }× B_{RE} _{ } ) ) 
9’b10_000_01_01  9’b10_000_01_01 
Kw: 2’b10  C: Additional complex number added independently on the Real and Imaginary side 
Complex Multiplication with Addition Equation  OPMODE_RE  OPMODE_IM 

P_{RE} + j P_{IM} = ( RND_{RE} + j RND _{IM} ) + ( ( A_{RE} + j A_{IM } ) × ( B_{RE} + j B_{IM } ) ) = ( RND + ( A_{RE} × B_{RE}  A_{IM }× B_{IM} _{ } ) ) + j ( RND + ( A_{RE} × B_{IM} + A_{IM }× B_{RE} _{ } ) ) 
9’b11_000_01_01  9’b11_000_01_01 
Kw: 2’b11  RND: Additional complex parameter (defined at compile time) used mostly for rounding. Parameter added independently on the Real and Imaginary side. 
ALUMODE Control
ALUMODE controls the operations performed by the final ALU (see the table in ALUMODE Inputs for details). ALUMODE_RE controls the operation performed by the ALU in the Real part of the DSPCPLX, similarly ALUMODE_IM with the Imaginary part.
For the main operations summarized in the previous OPMODE section (complex multiplication, complex multiplication with accumulation, and complex multiplication with addition) it is required that ALUMODE_RE = ALUMODE_IM = 4'b0000. In some other cases it might be necessary to set ALUMODE_RE ≠ ALUMODE_IM. The following shows an example operation:
P_{RE} + j P_{IM} = ( C_{RE}  j C_{IM} ) + ( ( A_{RE} + j A_{IM } ) × ( B_{RE} + j B_{IM } ) ) =
( C_{RE} + ( A_{RE} × B_{RE}  A_{IM }× B_{IM} _{ } ) ) + j ( C_{IM} + ( A_{RE} × B_{IM} + A_{IM }× B_{RE} _{ } ) )
Port  Description 

OPMODE_RE = 9'b00_011_01_01  Mux: X,Y = M 
Mux: Z = C  
OPMODE_IM = 9'b00_011_01_01  Mux: X,Y = M 
Mux: Z = C  
ALUMODE_RE = 4’b0000  P_{RE} = Z_{RE} + W_{RE} + X_{RE} + Y_{RE} + C_{INRE } 
ALUMODE_IM = 4’b0001  P_{IM} = Z_{IM} + W_{IM} + X_{IM} + Y_{IM} + C_{INIM }  1 
CIN_RE = 1’b0  P_{RE} = C_{RE} + M_{RE} 
CIN_IM = 1’b1  P_{RE} = C_{IM} + M_{IM} 
(CIN_IM = 1’b1 to compensate the 1 introduced by the ALUMODE_IM selection) 
 Use the OPMODE selection as described above to define the X,Y,Z,W multiplexers input/output relationships.
 See the table in ALUMODE Inputs and replace the output values for the X,Y,Z,W multiplexers in the equations as described in the previous step.