Using the cascade paths to implement adders significantly improves power consumption and speed. The maximum number of cascades in a path is limited only by the total number of DSP58s in one column on the chip. For more information, see Device Resources.
Important: The height of the DSP column can differ between devices and must be considered when porting designs.
Spanning columns is possible by taking the bus output from the top of one DSP column and adding CLB slice pipeline registers to route this bus to the C input of the bottom DSP58 of the adjacent DSP column. Alignment of input operands is also necessary to span multiple DSP columns.