The OPMODE, ALUMODE, and CARRYINSEL port logic support flow through or registered input control signals. Multiplexers controlled by configuration bits select flow through or optional registers. The control port registers allow you to trade off increased clock frequency (i.e., higher performance) versus data latency. The registers have independent clock enables and resets. The OPMODE and CARRYINSEL registers are reset by RSTCTRL. The ALUMODE is reset by RSTALUMODE. The clock enables and the OPMODE, ALUMODE, and CARRYINSEL port logic are shown in the following figure.
Figure 1. OPMODE, ALUMODE, and CARRYINSEL Port Logic