The basic parallel architecture, illustrated in the following figure, is referred to as the direct form type 1 filter. The final stages of the adder tree structure is usually where the performance bottleneck could increase cost, logic, and power. The adder cascade implementation accomplishes the post addition process with minimal silicon resources by using the cascade path within DSP58.
This structure implements the general FIR filter equation of a summation of products as defined in the following equation.
In the above equation, a set of N coefficients is multiplied by N respective data samples. The results are summed together to form an individual result. The values of the coefficients determine the characteristics of the filter (for example, a low-pass filter).
Other more optimal solutions for parallel filter architectures are covered in the following sections.