For symmetric FIR filter coefficients, the capable sample rate performance of a MACC FIR filter can be doubled (assuming the same clock speed). By rearranging the following FIR filter equation in the case of even number of taps, the coefficients are exploited as follows.
The following figure shows the architecture for a symmetric MACC FIR filter.
There are limitations to using the symmetric MACC FIR filter. The data (to A and D ports) and coefficients (to B port) are limited to 27 and 24 bits to fit into one DSP58.
Along with the three memory ports, additional filter resources are required to support symmetry. The control portion increases in resource utilization because the data is read out of one port in a forward direction and in reverse on the second port. This technique must only be used when extra sample rate performance is required.
The reference design files associated with this use case are available in the symmetric_macc_FIR directory in the associated design archive file, am004-versal-dsp-engine.zip.