Similar to the MACC FIR filters where symmetry was examined, exploiting symmetry is extremely powerful in parallel FIR filters because it halves the required number of multipliers, which is advantageous due to the finite number of DSP58s. The following equation is valid in the case of even number of taps and demonstrates how the data is pre-added before being multiplied by the single coefficient.

The following figure shows the implementation of a symmetric systolic FIR filter.

Figure 1. Symmetric Systolic FIR Filter

Note: The pre-adders (shaded in gray) in
DSP58 are used instead of implementing them in the programmable logic (PL). The register
delays in the input buffer time series are implemented as SRL16 and are spread evenly
across the DSP58s.

Coding examples are available in Language Templates with the Vivado® Integrated Design Environment (IDE) 2020.2 version.