Two-Input Logic Unit or Three-Input XOR Special Case

Versal ACAP DSP Engine Architecture Manual (AM004)

Document ID
AM004
Release Date
2022-09-11
Revision
1.2.1 English

The capability to perform an addition, subtraction, and simple logic functions in DSP58 exists through the use of a second-stage, four-input adder. The following table lists the logic functions that can be implemented in the second stage of the four input adder/subtracter/logic unit. The table also lists the settings of the OPMODE and ALUMODE control signals.

Setting OPMODE[3:2] to 00 selects the default 0 value at the Y multiplexer output. OPMODE[3:2] set to 10 selects all 1s at the Y multiplexer output. OPMODE[1:0] selects the output of the X multiplexer, OPMODE[6:4] selects the output of the Z multiplexer. For two-input or three-input logic operations, OPMODE[8:7] must be set to 00 for the default all 0s value at the W multiplexer output.

An XOR3 can be built by setting the OPMODE[3:2] to 11, selecting the C input at the Y multiplexer output. The XOR3 is only valid for ALUMODE[3:0] = 0100, as shown in the following table.

Table 1. OPMODE and ALUMODE Control Bits Select Logic Unit Outputs
Logic Unit Mode OPMODE[3:2] ALUMODE[3:0]
3 2 3 2 1 0
X XOR Z 0 0 0 1 0 0
X XNOR Z 0 0 0 1 0 1
X XNOR Z 0 0 0 1 1 0
X XOR Z 0 0 0 1 1 1
X AND Z 0 0 1 1 0 0
X AND (NOT Z) 0 0 1 1 0 1
X NAND Z 0 0 1 1 1 0
(NOT X) OR Z 0 0 1 1 1 1
X XNOR Z 1 0 0 1 0 0
X XOR Z 1 0 0 1 0 1
X XOR Z 1 0 0 1 1 0
X XNOR Z 1 0 0 1 1 1
X OR Z 1 0 1 1 0 0
X OR (NOT Z) 1 0 1 1 0 1
X NOR Z 1 0 1 1 1 0
(NOT X) AND Z 1 0 1 1 1 1
X XOR Y XOR Z 1 1 1 0 1 0 0
  1. Valid when Y multiplexer selects C input.