CLB Architecture

Versal ACAP Configurable Logic Block Architecture Manual (AM005)

Document ID
AM005
Release Date
2023-02-28
Revision
1.2 English

The CLB is the main resource in each VersalĀ® device and implements programmable combinational logic, sequential logic, and logic paths. These features enable high functionality and routability.

The following figure shows a high-level block diagram of the CLB. There are two CLB types, one with super long line (SLL) connections, and one without. Each CLB contains equal numbers of LUTRAM and SRL-capable LUTs. Only one LUT type can be used in a SLICEM.

Figure 1. CLB Block Diagram

The following figure shows a Versal device SLICEL/SLICEM. Note the IMUX registers, the carry lookahead logic which now contain fast lookahead multiplexers, and input and output multiplexers before and after the flip-flops. The multiplexers after the flip-flops are new to Versal devices. Some of the inputs to the input multiplexer are from the SLL connections.

Figure 2. SLICEL/SLICEM Block Diagram