Differences between Versal® adaptable computing acceleration platform (ACAP) configurable logic blocks (CLBs) and previous generations of UltraScale™ device CLBs are as follows:
- The CLB tile has been completely redesigned. The CLB has four times more logic capacity (32 LUTs/64 slice flip-flops as opposed to 8 LUTs/16 slice flip-flops in UltraScale devices). This results in more local routing for better performance and less general routing congestion.
- Dedicated LUT-LUT cascade paths now exist inside the CLB to reduce delays on multi-logic level paths as well as reduce external routing demands. In addition, the LUT-LUT cascade paths are leveraged to reduce cost and enable a more flexible carry logic structure.
- Super long line (SLL) connections are now part of the CLB (as opposed to being a dedicated column in previous architectures). There are no dedicated registers as the SLL connections rely on registering signals in the CLB.
- Wide function multiplexers (MUXF7, MUXF8, and MUXF9) are no longer implemented. Other LUTs are now used to implement wide multiplexing.
- There are now three outputs per LUT/FF pair instead of four. This enhances routability by increasing fanout per output.
- Dual LUT mode now supports 2 functions of up to 6 independent inputs.
- New cascade multiplexers enable new carry chains to start at bits 0 and 4.
- There is only one CLB type. One half of the LUTs in a CLB are capable of supporting LUTRAM and SRL configurations.
- LUTRAMs are simplified, having dedicated hardware to support 32 and 64 bit depths. Deeper LUTRAMs can be implemented using additional logic.
- Control sets for CLK and SR are at a coarser granularity, but CE stays the same.
- Output multiplexing in CLBs is new to Versal architecture. Each flip-flop is bypassable and can select one of several inputs. O6 comes straight out to interconnect and in carry mode also acts as carry_out. Both flip-flops receive O6 but each flip-flop only receives one of the O5 signals (O5_1 and O5_2).
- Additional registers (IMUX registers) are embedded into the CLB and also exist in the local interconnect block for all hard blocks connected to programmable logic routing. They allow additional pipelining by breaking critical paths into smaller pieces to increase FMAX. They are also used to fix hold time violations by gating data for a half cycle. This frees up routing resources previously used for hold time fixing.