LUTRAM

Versal® architecture LUTRAMs are simplified compared to previous architectures. Notable changes are:

• LUTRAM cells are available for depths of 64 and 32. Anything deeper will be decomposed to a set of those cells and a multiplexer tree.
  • No high-order address decode circuitry, and there are six write address inputs to each LUT.
  • No MUXF7, MUXF8, MUXF9 bels. Deeper LUTRAMs can be implemented using additional logic.
  • Because hardware support for deeper LUTRAM configurations is reduced placement restrictions exist for clusters of LUTs/SRLs/LUTRAMs to achieve optimal performance.
• Support for dual-edge clocking.
• Dedicated LRAM_WE site input for LUTRAM write-enable.
• LUTRAMs or SRLs can be combined with logic LUTs in a SLICEM.

As previously discussed, one half of the LUTs in every CLB are LUTRAM and SRL-capable (see CLB Architecture, Figure 1). In LUTRAM mode, a LUT can be configured as a 32-bit or 64-bit RAM. In SRL mode, a LUT can be configured as a 32-bit or two 16-bit shift register. Distributed RAM can be combined to create LUTRAM or SRL blocks with various size and features.

Address line masking circuitry that exists on a per column of eight LUTs, not on a per LUT basis. This is new to Versal architecture. As a result software packs either SRLs, LUTRAMs, or LUTs in a 8-LUT cluster but not a combination of these. The 4-LUT clusters in a SLICEM are based on columns of LUTs. {A_M,C_M,E_M,G_M} is one cluster, and {B_M,D_M,F_M,H_M} is another. The clusters can contain LUTRAMs, SRLs, or regular logic LUTs. Combinations of more than one LUT type in a 4-LUT cluster are not allowed. Each half of the CLB can have LUTRAM or SRL but not both. If LUTRAM is used in one 8-LUT cluster, the other 8-LUT cluster on the same side can only be regular a LUT or LUTRAM. Similarly, if SRL is used in one 8-LUT cluster the other 8-LUT cluster on the same side can only be a regular LUT or SRL. LUTRAM and SRL can be in the same CLB but they have to be in different sides. Each 8-LUT cluster can only have regular LUTs, LUTs configured as LUTRAM, or LUTs configured as SRL. Combinations of other LUT types in an 8-LUT cluster are not allowed.

Another difference new to Versal architecture is the removal of wide function multiplexers (F7,F8,F9). These were previously used to enable hardened support for deeper LUTRAM and SRL modes. Soft logic (such as LUTs implemented as dynamic multiplexers) must be used for LUTRAMs greater than 64 bits deep as well as SRLs greater than 32 bits that use dynamic tap selection.

External LUTs are also necessary to create the write enable logic. Prior architectures used a hardened write decoder, which enables faster best case timing but no placement flexibility. By requiring the write enable logic to be soft, individual LUTs of a deeper LUTRAM configuration can be shuffled around within a slice or even placed in different slices (although each separate slice would require using the H-LUTs input pins for write address). The following figure illustrates these concepts for a 512x1 LUTRAM. Blue blocks are hardened logic in the CLE, while the red blocks are created from external LUTs. Enable signals are routed to bypass pins associated with each LUTRAM LUT.

Figure 1. Write Decoder

Versal architecture supports all LUTRAM modes supported in previous architectures. Distributed RAM can be combined in various ways to store larger amount of data. RAM elements are configurable to implement the following configurations:

• Single-Port 32 x (1 to 16)-bit RAM
• Dual-Port 32 x (1 to 4)-bit RAM
• Quad-Port 32 x (1 to 4)-bit RAM
• Simple Dual-Port 32 x (1 to 14)-bit RAM
• Single-Port 64 x (1 to 8)-bit RAM
• Dual-Port 64 x (1 to 4)-bit RAM
• Quad-Port 64 x (1 to 2)-bit RAM
• Octal-Port 64 x 1-bit RAM
• Simple Dual-Port 64 x (1 to 7)-bit RAM
• Single-Port 128 x (1 to 4)-bit RAM
• Dual-Port 128 x 1-bit RAM
• Quad-Port 128 x 1-bit RAM
• Single-Port 256 x (1 to 2)-bit RAM
• Dual-Port 256 x 1-bit RAM
• Single-Port 512 x 1-bit RAM

  There is dedicated hardware support for LUTRAM 32x1, 32x2, and 64x1. Anything larger requires soft logic created with LUTs to support read and write address decoding.