Primitives

Versal ACAP Configurable Logic Block Architecture Manual (AM005)

Document ID: AM005
Release Date: 2023-02-28
Revision: 1.2 English

Overview
Introduction to Versal ACAP
Navigating Content by Design Process
CLB Features
CLB Architecture
Differences from Previous Generations
CLB Resources
Overview
CLB Resources
IMUX Register
Look-Up Table
LUTRAM
Shift Registers
Storage Elements
Control Signals
Carry Logic
Primitives
LUT Primitives
SRL Shift Register Primitives
Distributed RAM Primitives
Carry Look-Ahead Logic Primitives
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
Revision History
Please Read: Important Legal Notices

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