The system monitor is controlled by the SYSMON_PMC register module. Software code accesses this register module to configure and control the system monitor. The registers also provide a way to read results and set interrupt alarms. Enabled interrupts can generate a system interrupts. System interrupts are routed to the PS and PMC.
In the PMC/PS, the register module is memory-mapped at base address
0xF127_0000. This is a 32-bit APB programming interface attached to
the PMC interconnect. Accesses to the register module are routed through the Xilinx peripheral protection unit for the PMC (PMC_XPPU) before reaching
the system monitor. This programming interface can potentially be reached by any
processor in the system, including processors instantiated in the PL.
A PL processor can access the register module programming interface by attaching itself to a PL-to-PS AXI interface (e.g., S_AXI_LPD). This path also requires the LPD to be powered-up.
Versal ACAP Technical Reference Manual (AM011) provides information on the PMC/PS access paths, the 4 GB address map, and system interrupts.