Along with two temperature alarms (device and over-temperature) all the SYSMON can assert one up to 160 available voltage alarms (supply or external channels) in the system. Alarm assertion levels are fully customizable and interrupts can be enabled for both temperature alarms and voltage alarms. When averaging is enabled for an alarm, the alarm always asserts on the averaged value, rather than a single sample.
Voltage Alarms
Alarms enabled for voltage monitoring (supply and external inputs) commonly use window mode, in which the alarm is asserted if a reading falls above the upper threshold or below the lower threshold (see the previous figure). The ISR register will assert and remain asserted when an alarm condition occurs. Writing the a '1' to the alarm bit will clear the register's alarm when the alarm condition is no longer present. The CIPS wizard offers a GUI to configure the various registers used to set thresholds and enable alarms, SUPPLY0_TH_UPPER through SUPPLY159_TH_UPPER, SUPPLY0_TH_LOWER through SUPPLY159_TH_LOWER, ALARM_CONFIG, ALARM_REG0 through ALARM_REG5. Alarm assertion is indicated through the ALARM_FLAG0 through ALARM_FLAG4 and interrupts can be enabled to indicate an alarm occurrence. For additional details on these registers, see the SYSMON Registers section and refer to the SYSMON_PMC module in the Versal Adaptive SoC Register Reference (AM012).
Temperature Alarms
Because temperature concerns tend to be related to over-temperature, the temperature alarm typically uses the alarm mode called Hysteresis mode. Hysteresis mode asserts the alarm above a high temperature threshold, but uses the lower alarm threshold to deassert the alarm. The ISR register will assert and remain asserted when an alarm condition occurs. Writing the a '1' to the alarm bit will clear the register's alarm when the alarm condition is no longer present. This can be convenient in applications that reduce device function at high temperature only to resume when a sufficiently cool device temperature is achieved. See the following temperature alarm behavior diagram for an illustration of the alarm assertion behavior. As with voltage mode alarms, averaged values trigger alarm behavior.
Unlike the voltage alarms, the temperature alarms are always enabled and have a dedicated alarm register. Temperature Alarms are asserted in the ISR register, while DEVICE_TEM_TH_LOWER, DEVICE_TEMP_TH_UPPER, OT_TEMP_TH_LOWER and OT_TEMP_TH_UPPER define the temperature alarm behavior. For additional details on these registers and associated drivers, see the SYSMON Registers section and refer to the SYSMON_PMC module in the Versal Adaptive SoC Register Reference (AM012).
