Analog Input Description

Versal ACAP System Monitor Architecture Manual (AM006)

Document ID
AM006
Release Date
2022-05-17
Revision
1.3 English

In Versal architecture, the SYSMON analog input channels consist of a sampling switch and sampling capacitor used to acquire the analog input signal for a conversion. During the ADC acquisition phase, the sample switch is closed and the sampling capacitor is charged up to the voltage of the analog input. The sampled signal must settle during the acquisition phase, which is 1.6 μs, with an additional sampling period (3.4 μs) of settling time present when using an external multiplexer. The ADC has 10-bit resolution, so to allow for margin, 12-bit settling of the input signal is targeted during the acquisition phase. To ensure adequate settling time, a maximum total source impedance of 5 kΩ for dedicated and auxiliary inputs to ensure adequate settling times. When using an anti-aliasing filter, note that the impedance of the filter adds to the source impedance so care must be taken to ensure that the total remains within the limit.

Any additional external resistance, such as the anti-alias filter or resistor divider, increases the acquisition time requirement due to the increased RMUX value in the first equation. When using an anti-aliasing filter, the additional loading it presents to the input signal reduces the max source impedance, to achieve 12-bit settling, to 700Ω.

For more information and design considerations for driving the ADC inputs, see Driving the Xilinx Analog-to-Digital Converter (XAPP795).