Differences from Previous Generations

Versal ACAP System Monitor Architecture Manual (AM006)

Document ID
Release Date
1.3 English

The SYSMON block has been redesigned in VersalĀ® architecture to give full-featured support for all supply sensors. In Versal architecture, the SYSMON only exists in the processing system (PS) block as a feature of the platform management controller (PMC), with measurement capability extending across the whole device. Internal access to the SYSMON readings register map are available through memory-mapped registers, which can also be accessed through the external JTAG, I2C, or PMBus interfaces. Additional differences include:

  • Samples are stored in PMC memory-mapped registers. There is no dedicated interface to the SYSMON through the PL.
  • Scaled ADC architecture allows 160 channels sampling capability at 8 kSPS.
  • The ADC architecture is scaled such that regardless of how many channels are monitored, an 8 kSPS sample rate can be achieved.
  • Register-based status bits with interrupt capability inform the availability of new results, replacing PL based EOS and EOC status ports in previous architectures.
  • External analog inputs are available in multiplexed I/O (MIO) and high-density I/O (HDIO) banks.
  • External analog input selection is completely flexible within a MIO or HDIO bank, meaning that there are not strict channel pairs (i.e., any pin in the same MIO or HDIO bank can be a P or N side associated with any other pin in the same bank).
  • All internal supply and bank voltages can be monitored.
  • All channels are full-featured with unique alarm thresholds and averaging.
  • Alarms are interrupt-capable status registers rather than dedicated signal ports
  • The configuration of the SYSMON must be controlled by the Control, Interface, and Processing IP in Vivado tools.
  • There are no fixed results register locations per channel. Registers are assigned to channels by the Control, Interface, and Processing IP in Vivado.
  • The temperature transfer function is internally applied and results are stored in signed, fixed-point format, Q8.7, directly reading Celsius.
  • Supply samples stored in floating-point format, directly reading voltage.
  • Shared-N and bus ground features reduce the package pins requirement for auxiliary analog inputs by sharing reference pins for unipolar operation.
  • PMBus and I2C interfaces are available only after the SYSMON has been configured.
  • PMC provides access to results through JTAG and AXI interfaces.
  • Dynamic reconfiguration port (DRP) access and dedicated alarm ports are no longer supported.
  • Improved noise immunity provides more accurate sampling when using internal reference.
  • Provides averaging function of up to 16 samples on all channels.