I2C Interface

Versal ACAP System Monitor Architecture Manual (AM006)

Document ID
AM006
Release Date
2022-05-17
Revision
1.3 English

The SYSMON located in the master super logic region (SLR) acts as a slave to the I2C interface. The I2C interface must be enabled and configured by the Control, Interface, and Processing IP in Vivado® tools. The SYSMON I2C slave address is user-defined through the Processor IP.

Access to the control and status registers is provided using I2C Write and Read transfers. I2C transfers data by the byte starting with the lowest byte first. Within the byte, the MSB is transferred first as shown in the following figure. I2C uses open-collector signaling, which allows bidirectional data on I2C_SDA. The following figure shows how I2C_SDA and I2C_SCLK are used to send a write to the SYSMON. The master and slave devices control the I2C interface at different times during a transfer because I2C_SDA is bidirectional. Data is transmitted eight bits at a time with an acknowledge from the receiving device every eight bits. The transfer ends with the master device terminating the transfer with a stop command.

An I2C transfer packet consists of 56 bits which define the transaction direction, the bits 15 down to 2 of the memory-mapped register relative address being accessed, and a 32-bit data portion. A SYSMON I2C command has the structure shown in the following figure.

Figure 1. 56-bit I2C Command Format