SYSMON Registers

Versal Adaptive SoC System Monitor Architecture Manual (AM006)

Document ID
AM006
Release Date
2023-12-13
Revision
1.4 English

Unlike previous generations, the SYSMON in the AMD Versalâ„¢ device does not have fixed register mapping for configuring or reading voltage results from the SYSMON. To accommodate a large variety of sensors in different devices, the SYSMON contains memory-mapped registers that are configured by the Control, Interface, and Processing IP in Vivado tools. The IP is responsible for assigning attributes and results related to a register to a specific memory location. With up to 160 channels of memory-mapped registers, the SYSMON is capable of storing results for a large variety of sensor results. All the following references to specific channel values can reference comma separated variable file (CSV) produced by the CIPS wizard to indicate which measurement source mapping.

To simplify the use of the SYSMON registers, the unified platform includes examples and API under the sysmonpsv driver. Although register names are referenced this manual, the SYSMON memory-mapped registers are described in greater detail in the PMC_SYSMON_CSR Module module of the Versal Adaptive SoC Register Reference (AM012).

Channel Registers

Each voltage channel enabled by the Control, Interface, and Processing IP provides three registers of information: Current sample captured, the maximum sample captured, and the minimum sample captured. For each voltage channel, the IP automatically assigns a mapping for a given channel number from 0 to 159. The channel number stores current conversions, minimum, and maximum conversions in the SUPPLYXX, SUPPLYXX_MIN, and SUPPLYXX_MAX registers, where XX is a fixed channel number defined by the CIPS IP. As each channel finishes a conversion or averaging cycles, the user is alerted the NEW_DATA_FLAG0 through NEW_DATA4 registers. The NEW_DATA0 through NEW_DATA4 and NEW_DATA_FLAG0 through NEW_DATA_FLAG4 indicate that a new sample is available. If no voltage channels are enabled, these registers will not update. See Analog Channels for details on the format of the conversions.

For temperature, the channels DEVICE_TEMP, DEVICE_TEMP_MIN, and DEVICE_TEMP_MAX store the conversion information. The DEVICE_TEMP_MIN captures the lowest reading since reset (see STATUS_RESET) and DEVICE_TEMP_MAX captures the highest DEVICE_TEMP reading since reset (see STATUS_RESET). In addition to the DEVICE_TEMP registers, TEMP_LPD and TEMP_FPD are dedicated temperature sensors in the PS used at boot.

Alarms

Voltage alarms can be enabled through ALARM_REG0 through ALARM_REG4, with each bit in these registers representing a specific channel. As mentioned earlier, alarm lower thresholds are defined in registers SUPPLY0_TH_LOWER through SUPPLY159_TH_LOWER; while upper thresholds are defined in SUPPLY0_TH_UPPER through SUPPLY159_TH_UPPER. ALARM_FLAG0 through ALARM_FLAG4 indicate voltage alarm assertions for each of the 160 voltage based alarms in the SYSMON.

Temperature alarms are controlled by the OT_TEMP_TH_LOWER, OT_TEMP_TH_UPPER, DEVICE_TEMP_TH_LOWER, and DEVICE_TEMP_TH_UPPER registers. The ALARM_CONFIG register sets the alarm mode for the temperature sensors. Temperature alarm bits are found in the REG_ISR register.

Configuration Registers

Although the primary resource for configuring the SYSMON is through the CIPS wizard, there are some registers that can change SYSMON behavior. The CONFIG0 register in the SYSMON_PMC module allows the user to update averaging levels and configure I2C and PMBUS interfaces. The EN_AVG_REG0 through EN_AVG_REG4 registers enable voltage averaging on a per channel basis with averaging levels defined in the CONFIG0 register.

Interrupt Registers

New voltage samples are indicated through five registers, NEW_DATA_FLAG0 through NEW_DATA_FLAG4. Up to four channel interrupts can be assigned through the NEW_DATA_INT_SRC. The interrupts for both voltage and temperature results are enabled and controlled using the registers, ISR, IMR0, IMR1, IER0, IER1, IDR0, and IDR1.

Unlocking the Configuration Registers for Writing

The REG_PCSR_LOCK register must be written with the code 0xF9E8D7C6 to unlock the configuration registers to enable write operations. Writing any value to this register besides this code will re-lock the programming registers.