Additional Memory Resources

Versal ACAP Memory Resources Architecture Manual (AM007)

Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

In addition to block RAMs and UltraRAMs, the Versal ACAP includes small 64-bit RAMs distributed throughout the programmable logic, specialized RAMs in the processing system, and integrated memory controllers for access to external DDR memories. Details of these additional memory resources are available in the following documents:

  • See the Versal ACAP Configurable Logic Block Architecture Manual (AM005) for small (64-bit) distributed RAMs in the programmable logic.
  • See the Versal ACAP Technical Reference Manual (AM011) for processing system on-chip memory (OCM), tightly coupled memories (TCM), accelerator RAM (XRAM), and controller interfaces to external non-volatile memories. The OCM and XRAM can be accessed from the programmable logic through AXI interfaces.
  • See the Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313) for the integrated memory controller interface to external DDR memories.

See the Versal Architecture and Product Data Sheet: Overview (DS950) for availability and quantities of block RAM, UltraRAM, and additional memory resources in each Versal ACAP.