Address Bit Decoding

Versal ACAP Memory Resources Architecture Manual (AM007)
Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English
  • Row 1 Multicast

    ADDR18:15 = 0011 multicast to columns 1 + 2

    ADDR18:15 = 0101 multicast to columns 1 + 3

    ADDR18:15 = 0110 multicast to columns 2 + 3

    ADDR18:15 = 0111 multicast to columns 1 + 2 + 3

    ADDR18:15 = 1101 multicast to columns 1 + 2 + 4

    etc.

    ADDR18:15 = 1111 multicast to columns 1 + 2 + 3 + 4

  • Row/Column Addr

    ADDR22:19 = 0001 – 0011 rows 2, 3, 4, column 1

    ADDR22:19 = 0101 – 0111 rows 2, 3, 4, column 2

    ADDR22:19 = 1001 – 1011 rows 2, 3, 4, column 3

    ADDR22:19 = 1101 – 1111 rows 2, 3, 4, column 4

Note: For broadcast write applications, it is possible to set "SELF_MASK/SELF_ADDR" to non-unique values. This is only allowed if a port is used as a write-only port. This allows multiple UltraRAMs to be written in a single transaction.

The Versal device is supported by the Vivado Design Suite, which includes several code templates to help target the available silicon resources. There are three methods of RTL design entry to use the UltraRAM memories:

  • Use the Xilinx Parameterized Macros (XPM)
  • Infer an RTL memory and use the ram_style attribute set to "ultra."
  • Instantiate the device primitive.

Examples for these methods are in the Vivado language templates accessible from the main Vivado tools menu by selecting Tools > Language Templates.

XPM is the most effective method to obtain expected results with a high degree of customization.